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LP3921 数据表(PDF) 14 Page - Texas Instruments |
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LP3921 数据表(HTML) 14 Page - Texas Instruments |
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14 / 44 page ![]() 60 ms PS_HOLD LDO1 LDO2 PWR_ON RESET LDO4,5,6 LDO3 LDO7 PS_HOLD needs to be asserted while PWR_ON is high. 30 ms Debounce time Note: Serial I/F commands only take place after PS_HOLD is asserted. 87% Reg 87% Reg < 200 Ps RX_EN, TX_EN, TCXO_EN I 2 C Control LP3921 SNVS580A – AUGUST 2008 – REVISED MAY 2013 www.ti.com TECHNICAL DESCRIPTION DEVICE POWER UP AND SHUTDOWN TIMING Figure 2. Device Power Up Logic Timing: PWR_ON 14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LP3921 |
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