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SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

Start Condition

Stop Condition

SDA

SCL

LP8557, LP85571

www.ti.com

SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015

Programming (continued)

8.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the I2C session (see Figure 33). A START

condition is defined as SDA transitioning from HIGH to LOW while SCL is HIGH. A STOP condition is defined as

SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP

conditions. The I2C bus is considered busy after a START condition and free after a STOP condition. During data

transmission the I2C master can generate repeated START conditions. A START and a repeated START

condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock

signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW.

Figure 33. Start And Stop Conditions

After the START condition, the I2C master sends the 7-bit address followed by an eighth read or write bit (R/W).

R/W = 0 indicates a WRITE, and R/W = 1 indicates a READ. The second byte following the chip address selects

the register address to which the data is written. The third byte contains the data for the selected register.

8.5.1.3

Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Figure 34. Bit Transfer

Each data transaction is composed of a START Condition, a number of byte transfers (set by the software) and a

STOP Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

8.5.1.4 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

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