LP85571 datasheet(28/49 Pages) TI2

28 / 49 page

LP8557, LP85571

SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015

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8.6.1.7 PGEN

Address: 0x12h

Reset: 0x29h (LP8557I)

PFSET

—

THRESHOLD

PRFEQ[2:0]

Bits

Field

Type

Default

Description

PFSET

R/W

Set PWM output frequency via the FSET pin.

0 = PWM output frequency is set with PRFEQ bits. (Default)

1 = PWM output frequency is set with an external, RFSET, resistor.

6:3

reserved

R/O

0101b

5:3

THRESHOLD

R/W

EPROM

Adaptive dimming threshold. PWM dimming is used below threshold, and current

dimming is used above threshold.

000 = 100% current diming

001 = PWM below 1.5625% (6-bit PWM)

010 = PWM below 3.125% (7-bit PWM)

011 = PWM below 6.25% (8-bit PWM)

100 = PWM below 12.5% (9-bit PWM)

101 = PWM below 25% (10-bit PWM)

110 = PWM below 50% (11-bit PWM)

111 = 100 %PWM below (12-bit PWM)

2:0

PFREQ

R/W

001b

PWM output frequency

000 = 4.9 kHz

001 = 9.8 kHz (Default)

010 = 14.6 kHz

011 = 19.5 kHz

100 = 24.4 kHz

101 = 29.3 kHz

110 = 34.2 kHz

111 = 39.1 kHz

The PFSET bit distinguishes how the PWM dimming frequency is set. On the LP8557I (PFSET = 0), the PWM

dimming frequency is 9.8 kHz by default. It may be re-configured via I2C interface by overriding PFREQ bits.

Note that re-configuration must be done every time the power on VDD pin is recycled.

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