6.5.5 SDQ Signaling

The single wire communication does not have a reference clock and is critical to adhere to stringent timing

protocols to maintain the data integrity. The timing protocol consists of four types of signaling:

1. Reset sequence with reset pulse and presence pulse

2. Write-zero timing sequence

3. Write-one timing sequence

4. Read-data timing sequence

The host initiates the communication by pulling the SDQ line low, except for the presence pulse which is initiated

by the responder devices on the SDQ bus. The responder devices can communicate at two different speeds:

standard speed and overdrive speed. The responder device by default only communicates at standard speed

unless the device is set into the Overdrive mode, in which case the responder device responds to commands

issued in the Overdrive timing (fast timing). All the timing waveforms shown below are applicable to both

Standard timing and Overdrive timing.

All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0,

or to begin the start frame for a bit read. Figure 6-16 shows the initialization timing, whereas Figure 6-17, Figure

6-18, and Figure 6-19 show that the host initiates each bit by driving the SDQ bus low for the start period, tW1L /

tW0L / tRL. After the bit is initiated, either the host continues controlling the bus during a WRITE, or the responder

device controls the bus to transfer a 0 bit during a READ.

6.5.5.1 RESET and PRESENCE PULSE

During the reset sequence, if the SDQ bus is driven low for more than 120 μs, the responder devices can be

reset. If the SDQ bus is driven low for more than 480 μs, then the responder devices reset and indicate that the

devices are ready for communication by responding with a presence pulse. If the TMF0008 is in Overdrive mode

and a tRSTL duration of 480 μs or longer is issued by the host, the device exits the Overdrive mode returning

to standard speed. If the device is in Overdrive mode and tRSTL is no longer than 80 μs, the device remains in

Overdrive mode. If the device is in Overdrive mode and tRSTL is between 80 μs and 480 μs, the device resets,

but the communication speed is undetermined.

Figure 6-16 shows the reset pulse initiated by host and Response Presence Pulse initiated by TMF0008 (target).

VPUP

VTH

VTL

tRSTL

Host drives SDQ

Device drives SDQ

High Impedance, external pull-up

tPDH

tPDL

tREC

tRSTH

tPDS

tF

Figure 6-16. Reset Sequence Timing Diagram

TMF0008

SLVSIV3 – JULY 2025

www.ti.com

22

Submit Document Feedback

Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: TMF0008