6.5.5.2 Write-Read-Time Slots

The single wire interface communication does not have a reference clock. Hence, all communication is

performed asynchronously with fixed time slot (tSLOT) and variable pulse width to indicate logic 0 and 1. In

idle state, the external pullup resistor holds the line high. Whether all bit communication is a write or a read, both

are initiated by the host by driving the data line low and the bit value is decoded as the time for which the data

line is held low.

Even though the communication is one bit at a time, the data exchanged between the host and device is

performed at byte boundary. Every byte is sent least significant bit first. The device behavior is not verified when

incomplete bytes are sent.

The Write-One timing diagram in Figure 6-17 shows that the host initiates the write-one transmission by pulling

the SDQ bus low for the tF + tW1L - tε duration and then releasing the SDQ bus. Similarly, the Write-Zero timing

diagram in Figure 6-18 shows that the host initiates the write-zero transmission by the pulling the SDQ bus low

for the tF + tW0L - tε duration and then releasing the SDQ bus. As the voltage on the SDQ bus falls below the

threshold VTL, the device starts the internal timing generator that determines when the SDQ line is sampled

during a write-time slot to determine whether the bit is 1 or 0. The device samples the SDQ line some time

between the max tW1L duration and the min tW0L duration.

The read-data timing diagram in Figure 6-19 shows that the host initiates the transmission of the bit by pulling

the SDQ bus low for the tF + tRL duration. The device then responds by either driving the SDQ bus low to

transmit a READ 0 or releasing the SDQ bus to transmit a READ 1. The host must factor the rise time due to the

pullup resistor and bus capacitance, to determine the sampling window to sample the bit level sent by the device

or driving the next read bit time slot.

VPUP

VTH

VTL

tW1L

Host drives SDQ

High Impedance, external pull-up

tSLOT

tF

tε

Figure 6-17. Write-One Timing Diagram

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