5.5 Electrical Characteristics

Minimum and Maximum specifications apply from TA of -10°C to 85°C. Typical specifications are at 25°C and VPUP = 3.3 V

and 5 V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IO Pin: General Data

VPUP

Pull-up Voltage

±5% variation

3.13

3.3

3.46

V

4.75

5

5.25

V

RPUP

Pull-up Resistance

Notes (1),(2),(5)

500

Ω

CCABLE

Cable Capacitance

Notes (4),(11)

1.7

nF

CIO

Input Capacitance

Notes (3),(4)

2000

pF

IL

Input Load Current

Note (6)

7

14

µA

VIL

Input Low Voltage

Note (7)

0.5

V

VOL

Output Low Voltage

Measured with RPUP = 500Ω,

VPUP = 3.3V

0.4

0.5

V

Measured with RPUP = 500Ω,

VPUP = 5V

0.4

0.5

V

VTL

High-to-Low Switching threshold

(Notes (4),(5),(8))

VPUP = 3.3V

0.84

1.72

V

VPUP = 5V

2

3

V

VTH

Low-to-High Switching Threshold

(Notes (4),(5),(9))

VPUP = 3.3V

1.64

2.75

V

VPUP = 5V

3.2

4.3

V

VHY

Switching Hysteresis

(Notes (4),(5),(10))

VPUP = 3.3V

0.44

1.1

V

VPUP = 5V

0.9

1.3

V

(1)

Maximum allowable pull-up resistance is dependent on the number of devices connected and the recovery time. The specified value is

assuming six devices are connected in the system and minimum recovery time.

(2)

Resistance tolerance to be within 1% or less.

(3)

Maximum Capacitance value represents the internal parasitic capacitance when VPUP is first applied. Once the parasitic charge

storage capacitance is charged, normal logic transitions are not affected.

(4)

Specified by design, characterization or simulation only. Not production tested.

(5)

VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, single-wire timing, and capacitive

loading on SDQ pin. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and

VHY.

(6)

Applicable when SDQ is HIGH (at VPUP) and the device is in idle mode (no digital activity or memory access). The numbers indicates

the stand-by current consumption.

(7)

The voltage on SDQ needs to be less or equal to VILMAX at all times the host is driving SDQ to a logic 0 level.

(8)

Voltage below which, during a falling edge on SDQ, logic 0 is detected.

(9)

Voltage above which, during a rising edge on SDQ, logic 1 is detected.

(10) After VTH is crossed during a rising edge on SDQ pin, the voltage on SDQ must drop by at least VHY to be detected as logic 0.

(11) System requirement.

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TMF0008

SLVSIV3 – JULY 2025

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