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STA380WS 数据表(PDF) 33 Page - STMicroelectronics |
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STA380WS 数据表(HTML) 33 Page - STMicroelectronics |
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33 / 48 page  DocID024426 Rev 1 33/48 STA380WS Register description 6.2 Volume control registers (addr 0x06 to 0x09) 6.2.1 Mute/line output configuration register (addr 0x06) Master mute Channel mute D7 D6 D5 D4 D3 D2 D1 D0 Reserved C2M C1M MMUTE 00000000 Table 39. Master mute Bit R/W RST Name Description 0 R/W 0 MMUTE 0: normal operation 1: all channels are in mute condition Table 40. Channel mute Bit R/W RST Name Description 1 R/W 0 C1M Channel 1 mute: 0: not muted, it is possible to set the channel volume 1: hardware muted 2 R/W 0 C2M Channel 2 mute: 0: not muted, it is possible to set the channel volume 1: hardware muted Obsolete Product(s) - Obsolete Product(s) |
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