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STA380WS 数据表(PDF) 41 Page - STMicroelectronics |
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STA380WS 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 48 page  DocID024426 Rev 1 41/48 STA380WS Application information Figure 12. PLL filter circuit 7.3 Typical output configuration Figure 13 below shows a typical output configuration used for BTL stereo mode. Figure 13. Typical BTL configuration 100p F FIL T E R _ P L L 68 0 p F 4.7 n F 2K 2 100p F FIL T E R _ P L L 68 0 p F 4.7 n F 2K 2 BE A D P L L_G N D G ND_ DIG 100p F FIL T E R _ P L L 68 0 p F 4.7 n F 2K 2 100p F FIL T E R _ P L L 68 0 p F 4.7 n F 2K 2 BE A D BE A D P L L_G N D G ND_ DIG 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 LEFT 100nF 6.2 OUT1A OUT1B 6.2 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 RIGHT 100nF 6.2 OUT2A OUT2B 6.2 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 LEFT 100nF 6.2 OUT1A OUT1B 6.2 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 LEFT 100nF 6.2 OUT1A OUT1B 6.2 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 RIGHT 100nF 6.2 OUT2A OUT2B 6.2 22uH 22uH 100nF 100nF 470nF 330pF 100nF 22 RIGHT 100nF 6.2 OUT2A OUT2B 6.2 Obsolete Product(s) - Obsolete Product(s) |
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