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CB45000 数据表(PDF) 4 Page - STMicroelectronics

部件名 CB45000
功能描述  HCMOS6 STANDARD CELLS
PDF  16 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

CB45000 数据表(HTML) 4 Page - STMicroelectronics

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CB45000 SERIES
4/16
®
LIBRARY
The CB45000 Series library is organized into four
categories:
s
SSI cell library
s
IO Cell library
s
Macrofunctions
s
Module generators
SSI CELL LIBRARY OVERVIEW
The design of the CB45000 family has been
optimized to allow extremely high density, high
speed and low power designs. For these reasons
a wide range of cells with different ranges of
driving capability are available in the library.
The library cells have been optimized in term of
functional and electrical parameters in order to
have:
s
Good balancing
s
Maximum speed
s
Optimum Threshold voltage
s
Symmetric Vdd/Vss Noise margin
s
Minimum Power-Speed figure
The
geometrical
aspect
of
the
cells
was
configured to allow extremely dense design, fully
exploiting the features of the Place and Route
tool in terms of horizontal and vertical routing
grids. For Place and Route, up to five levels of
metal are utilized. Intracell wiring is limited as far
as possible to first metal, with second, third and
fourth metal levels dedicated to interconnect
wiring and power distribution. The fifth metal is
used for power and clock bussing.
CORE LOGIC
The propagation delays shown in the CB45000
data book are given for nominal processing, 3.3V
operation, and 25 C temperature conditions.
However there are additional factors that affect
the delay characteristics of the macrocells. These
include loading due to fanout and interconnect
routing, voltage supply, junction temperature of
the device, processing tolerance and input signal
transition time.
Prior to physical layout, the design system can
estimate the delays associated with any critical
path. The impact of the placement and routing
can be accurately RC back annotated from the
layout for final simulations of critical timing. The
effects of junction temperature, (KT) and voltage
supply
(KV)
on
the
delay
numbers
are
summarized in Table 2 and Table 2. A third factor,
is
associated
with
process
variation.
This
multiplier has a minimum of 0.8 and a maximum
of 1.2.
10 Êm
Figure 2. ND2 Core Cell
Table 1 Junction Temperature Multipliers
Temperature oCKT
-55
0.77
-40
0.83
25
1.00
70
1.13
85
1.17
125
1.27



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