VDDQ

PVIN

AVIN

1

2

3

4

8

7

6

5

VSENSE

VREF

SD

GND

VTT

VDDQ

PVIN

AVIN

1

2

3

4

8

7

6

5

VSENSE

VREF

SD

GND

VTT

GND

LP2998, LP2998-Q1

www.ti.com

SNVS521K – DECEMBER 2007 – REVISED AUGUST 2014

6 Pin Configuration and Functions

SO PowerPAD

8-LEAD DDA

TOP VIEW

SOIC

8-LEAD D

TOP VIEW

Pin Functions

PIN

NUMBER

TYPE

DESCRIPTION

1

GND

Ground

2

SD

Shutdown

3

VSENSE

Feedback pin for regulating VTT.

4

VREF

Buffered internal reference voltage of VDDQ/2

5

VDDQ

Input for internal reference equal to VDDQ/2

6

AVIN

Analog input pin

7

PVIN

Power input pin

8

VTT

Output voltage for connection to termination resistors

EP

Exposed pad thermal connection. Connect to Ground.

6.1 Pin Descriptions

AVIN AND PVIN

AVIN and PVIN are the input supply pins for the LP2998. AVIN is used to supply all the internal control circuitry. PVIN,

however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the

capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the

maximum continuous output current because of output RDSON limitations at voltages close to VTT. The disadvantage

of high values of PVIN is that the internal power loss will also increase, thermally limiting the design. For SSTL-2

applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This eliminates the

need for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be

equal to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3 V to prevent

the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the

thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where VTT is tri-stated and

VREF remains active.

VDDQ

VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated

from a resistor divider of two internal 50 k

Ω resistors. This ensures that VTT will track VDDQ / 2 precisely. The optimal

implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 2.5 V rail at

the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely

without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be a 2.5 V signal, which will

create a 1.25 V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT over

temperature).

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Product Folder Links: LP2998 LP2998-Q1