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LP2998MA/NOPB 数据表(PDF) 11 Page - Texas Instruments

部件名 LP2998MA/NOPB
功能描述  LP2998/LP2998-Q1 DDR Termination Regulator
PDF  42 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

LP2998MA/NOPB 数据表(HTML) 11 Page - Texas Instruments

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background image
-
+
VTT
PVIN
VDDQ
SD
GND
AVIN
VSENSE
50k
50k
+
-
VREF
LP2998, LP2998-Q1
www.ti.com
SNVS521K – DECEMBER 2007 – REVISED AUGUST 2014
8 Detailed Description
8.1 Overview
The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for
termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus
termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent
response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current
and transient peaks up to 3 A in the application as required for DDR-SDRAM termination.
8.2 Functional Block Diagram
8.3 Feature Description
The LP2998 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and
SSTL-18. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to
VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot
through. The LP2998 also incorporates two distinct power rails that separates the analog circuitry from the power
output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits
the LP2998 to provide a termination solution for DDR3-SDRAM and DDR3L-SDRAM memory.
8.4 Device Functional Modes
The LP2998 can also be used to provide a termination voltage for other logic schemes such as SSTL-3 or HSTL.
Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting
at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single
parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination
resistor. Typical values for RS and RT are 25 Ω, although these can be changed to scale the current
requirements from the LP2998. This implementation can be seen below in Figure 16.
Copyright © 2007–2014, Texas Instruments Incorporated
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Product Folder Links: LP2998 LP2998-Q1



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