M41ST85WMH6F datasheet(19/43 Pages) STMICROELECTRONICS

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M41ST85W

Clock operation

The eight byte clock register (see Table on page 20) is used to both set the clock and to

read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths

of seconds, seconds, minutes, and hours are contained within the first four registers.

Note:

A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to

“00,” and tenths/hundredths of seconds cannot be written to any value other than “00.”

Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY

ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle,

either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial

state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the

day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month and

years. The ninth clock register is the control register (this is described in the clock calibration

section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause

the oscillator to stop. If the device is expected to spend a significant amount of time on the

shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator

restarts within one second.

The eight clock registers may be read one byte at a time, or in a sequential block. The

control register (address location 08h) may be accessed independently. Provision has been

made to assure that a clock update does not occur while any of the eight clock addresses

are being read. If a clock address is being read, an update of the clock registers will be

halted. This will prevent a transition of data during the READ.

3.1

Power-down time-stamp

When a power failure occurs, the halt update bit (HT) will automatically be set to a '1.' This

will prevent the clock from updating the TIMEKEEPER® registers, and will allow the user to

read the exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock

to update the TIMEKEEPER registers with the current time. For more information, see

application note AN1572.

3.2

TIMEKEEPER® registers

The M41ST85W offers 20 internal registers which contain clock, alarm, watchdog, flag,

square wave and control data. These registers are memory locations which contain external

(user accessible) and internal copies of the data (usually referred to as BiPORT™

TIMEKEEPER cells). The external copies are independent of internal functions except that

they are updated periodically by the simultaneous transfer of the incremented internal copy.

The internal divider (or clock) chain will be reset upon the completion of a WRITE to any

clock address.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). The update will resume either due to a stop condition or when

the pointer increments to a non-clock or RAM address.

TIMEKEEPER and alarm registers store data in BCD. control, watchdog and square wave

registers store data in binary format.

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