DC and AC parameters

M41ST85W

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DocID7531 Rev 12

Figure 19. Bus timing requirements sequence

AI00589

SDA

P

tSU:STO

tSU:STA

tHD:STA

SR

SCL

tSU:DAT

tF

tHD:DAT

tR

tHIGH

tLOW

tHD:STA

tBUF

S

P

Table 12. AC characteristics

Symbol

Parameter(1)

Min

Max

Unit

tSCL

SCL clock frequency

0

400

kHz

tBUF

Time the bus must be free before a new transmission can start

1.3

µs

tEXPD

EX to ECON propagation delay

15

ns

tF

SDA and SCL fall time

300

ns

tHD:DAT

(2)

Data hold time

0

µs

tHD:STA

START condition hold time (after this period the first clock pulse is generated)

600

ns

tHIGH

Clock high period

600

ns

tLOW

Clock low period

1.3

µs

tR

SDA and SCL rise time

300

ns

tSU:DAT

Data setup time

100

ns

tSU:STA

START condition setup time (only relevant for a repeated start condition)

600

ns

tSU:STO

STOP condition setup time

600

ns

1.

Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6 V (except where otherwise noted).

2.

Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.