Data Sheet

ADPA1120

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 6 of 19

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1 to 3, 7 to 9, 12, 13,

16 to 19, 21, 22, 24

to 28, 32

NIC

Not Internally Connected. The NIC pins are not connected internally. However, all data shown was measured with

the NIC pins connected to RF and DC ground externally.

4, 6

GND

Ground. The GND pins must be connected to RF and DC ground. See Figure 3 for the interface schematic.

5

RFIN

RF Input. The RFIN pin is AC-coupled in the signal path and is matched to 50Ω. See Figure 4 for the interface

schematic. If the RFIN pin is externally connected to a DC bias level other than 0 V, AC-couple the RFIN pin

externally because of the internal DC path to ground.

10

VREF

Reference Diode for Temperature Compensation of VDET RF POUT Measurements. See Figure 8 for the interface

schematic.

11, 14, 15

VDD1-2, VDD3, VDD4

Drain Bias Voltages. First, second, third and fourth stage drain bias. See Figure 7 for the interface schematic.

20

RFOUT

RF Output. The RFOUT pin is AC-coupled and is matched to 50Ω. See Figure 6 for the interface schematic.

23

VDET

Detector Diode to Measure RF POUT. POUT detection via the VDET pin requires the application of a DC bias

voltage through an external series resistor. Used in combination with the VREF pin, the difference voltage (VREF

voltage (VREF) − VDET voltage (VDET)) is a temperature compensated DC voltage that is proportional to the RF

POUT. See Figure 8 for the interface schematic.

29, 30, 31

VGG4, VGG3, VGG1-2

Gate Bias Voltages. First, second, third and fourth stage gate bias. See Figure 5 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to RF and DC ground.