Data Sheet

ADPA1120

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 16 of 19

BASIC CONNECTIONS

The basic connections for operating the ADPA1120 are shown in

Figure 49. Apply a power supply voltage between 14V and 20V to

the VDD1-2, VDD3, and VDD4 pins. Decouple the VGG1-2, VGG3,

VGG4, VDD1-2, VDD3, and VDD4 pins with the capacitor and

resistor values shown in Figure 49. The gate bias pins, VGG1-2,

VGG3, and VGG4, are used to bias the ADPA1120. Pin 1 to Pin 3,

Pin 7 to Pin 9, Pin 12, Pin 13, Pin 16 to Pin 19, Pin 21, Pin 22,

Pin 24 to Pin 28, and Pin 32 are designated as the not internally

connected (NIC) pins. Although these NIC pins are not internally

connected, the NIC pins were all connected to ground during the

characterization of the device.

Apply a voltage between −3V and −1V to the VGGx pins to set the

bias level and drain current. The ADPA1120 can support both con-

tinuous and pulsed operation; however, pulsed operation provides

better thermal management by pulsing either the gate voltage or

the drain voltage.

In gate pulsed mode, VDD is held at a fixed level (nominally 20V)

while the gate voltage is pulsed between −4V (off) and approxi-

mately −3V to −1V (on). The exact on level can be adjusted to

achieve the desired IDQ.

In drain pulsed mode, the VDD voltage is pulsed on and off while the

gate voltage is held at a fixed negative level between −3V and −1V.

Because high currents and voltages are being switched on and off,

a metal-oxide semiconductor field effect transistor (MOSFET) and a

MOSFET switch driver are required in the circuit. Large capacitors

are also required, which act as local reservoirs of charge, and these

capacitors help provide the drain current required by the ADPA1120

while maintaining a steady drain voltage during the on time of the

pulse.

The ADPA1120-EVALZ evaluation board package includes a plugin

pulser board that contains the required circuitry to implement drain

pulsed mode. See the ADPA1120-EVALZ user guide for more

information.

To safely turn power on, the VGGx pins must be set to −4V before

VDD is applied. After the VGGx pins are increased to achieve the

desired drain bias current, the RF input can be applied. Trigger the

RF source so that the RF is applied only during the time the drain

pulse is high. To safely turn power off, remove the RF input signal

and decrease the VGGx pins to −4V. VDD can then be decreased to

0V before increasing VGG1-2 to 0V.

Figure 49. Basic Connections