Data Sheet

ADPA1120

THEORY OF OPERATION

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Rev. 0 | 15 of 19

The ADPA1120 is a GaN power amplifier that delivers 36.5dBm

(4.5W) of pulsed power. The device consists of four cascaded gain

stages. A simplified block diagram is shown in Figure 48.

The positive bias voltage that applied to the VDD1-2, VDD3, and

VDD4 pins provides bias to the drains of the first, second, third and

fourth gain stages, respectively (a single common supply voltage

must be used). The negative DC voltages are applied to the

VGG1-2, VGG3, and VGG4 gates bias pins of the first, second,

third and fourth gain stages, respectively, to allow control of the

drain currents for each stage.

The recommended DC biasing results in a typical pulsed RF POUT

and PAE of 36.5dBm and 47%, respectively, across the band of

9.5GHz to 11.5GHz when the input power is 1dBm.

The ADPA1120 has single-ended RFIN and RFOUT ports that are

AC-coupled. The impedance of these ports are nominally 50Ω over

the 8GHz to 12GHz operating frequency range. Consequently, the

ADPA1120 can be directly inserted into a 50Ω system without the

need for external impedance matching components or AC coupling

capacitors.

A portion of the RF output signal (RFOUT) is directionally coupled

to a diode to detect the RF POUT. When the diode is DC biased

externally through a resistor, it rectifies the RF power and makes

it available as a DC voltage at VDET. To allow temperature com-

pensation of VDET, the reference DC voltage detected through an

identical diode that is not coupled to the RF power is available

on the VREF pin. The difference of VREF − VDET provides a temper-

ature-compensated detector voltage that is proportional to the RF

POUT.

The small signal gain drops significantly at −40°C because the

device is biased close to the transistor pinch-off voltage. At cold

temperatures, the pinch-off voltage shifts more positive as can be

seen in Figure 46. As a result, a more positive gate voltage is

required to turn on the transistor and have current flow. The gain

at small signal levels and cold temperatures are much lower than

room temperature; however, the performance at large signal levels

is as expected and shown in Figure 21.

The data in this data sheet was captured by setting the drain

current to a nominal IDQ, that is, 50mA. After this initial IDQ was

determined, the gate voltage was kept constant in subsequent

testing and operation. It is possible that the IDQ will increase by

some amount with continued operation at that fixed VGG gate volt-

age. Keeping the gate voltage constant during long-term operation

provides more consistent RF performance than keeping a nominal

IDQ constant.

Figure 48. Basic Block Diagram