Data Sheet

ADPA1120

APPLICATIONS INFORMATION

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Rev. 0 | 17 of 19

RECOMMENDED BIAS SEQUENCE

The recommended bias sequence for power‑up is as follows:

1. Connect all GND pins to ground.

2. Set the voltages on the VGG1-2, VGG3, and VGG4 pins to −4V.

3. Set the voltages on the VDD1-2, VDD3, and VDD4 pins to 20V.

4. Increase the voltages of the VGG1-2, VGG3, and VGG4 pins

from −3V to −1V to achieve the desired IDQ, nominally 50mA.

5. Apply the RF signal to the RFIN pin.

The recommended sequence for the transmit state during pow-

er‑down is as follows:

1. Turn off the RF signal.

2. Decrease the voltages of the VGG1-2, VGG3, and VGG4 pins

to −4V.

3. Set the voltages on the VDD1-2, VDD3, and VDD4 pins to 0V.

4. Set the voltages on the VGG1-2, VGG3, and VGG4 pins to 0V.

All measurements and data shown in this data sheet were taken

using the basic connections circuit (see Figure 49) and biased per

the conditions in this section, unless otherwise noted. The bias

conditions described in this section are the operating points rec-

ommended to optimize the overall device performance. Operation

using other bias conditions can result in performance that differs

from what is shown in the Typical Performance Characteristics

section. To obtain optimal performance while not damaging the de-

vice, follow the recommended biasing sequences described in this

section and adhere to the values shown in the Absolute Maximum

Ratings section.

DRAIN PULSING

To implement drain pulsed operation on the ADPA1120, apply a

negative voltage to the gate pins of the power amplifier while the

voltage on the drain pins are pulsed between 0V and 20V.

The power supplies used to provide the drain voltages to the

ADPA1120 must have a fast transient response to minimize voltage

droop.

Drain Pulsing Setup

Take the following steps to set up drain pulsing:

1. Connect all power supply, ground, and control signals to the

ADPA1120, see Figure 49.

2. To pulse the power amplifier, set the voltages on the VGG1-2,

VGG3 and VGG4 pins to −4V and set the voltages on the

VDD1-2, VDD3, and VDD4 pins to 20V.

3. Turn on the drain voltage pulse pins, VDD1-2, VDD3 and

VDD4, pulsing between 0V and 20V, 100μs, and 10% duty

cycle typical.

4. Adjust the voltages on the VGG1-2, VGG3 and VGG4 pins

between −3V and −1V until the target pulsed IDQ is reached

(nominally 50mA).

5. Apply the RF input signal.

GATE PULSING

To implement gate pulsed operation on the ADPA1120, apply a

pulsed negative voltage to the gate pins of the power amplifier while

the voltage on the drain pins are held constant.

The power supplies used to provide the drain voltages to the

ADPA1120 must have a fast transient response to minimize voltage

droop.

Gate Pulsing Setup

Take the following steps to set up gate pulsing:

1. Connect all power supply, ground, and control signals to the

ADPA1120, see Figure 49.

2. To pulse the power amplifier, set the voltages on the VGG1-2,

VGG3 and VGG4 pins to −4V and set the voltages on the

VDD1-2, VDD3 and VDD4 pins to 20V.

3. Turn on the gate voltage pulse pins, VGG1-2, VGG3 and

VGG4, pulsing between −4V and approximately −3V, 100μs,

and 10% duty cycle typical.

4. Adjust the gate voltage pulse high-voltage between −3V and

−1V to achieve the target pulsed IDQ (nominally 50mA) while

maintaining the pulse off voltage level at −4V.

5. Apply the RF input signal