IS25LE02GG-RHLA2:P-TY datasheet(101/187 Pages) ISSI

101 / 187 page

IS25LE02GG

IS25WE02GG

Integrated Silicon Solution, Inc.- www.issi.com

101

Rev. A1

10/02/2025

8.24 PROGRAM/ERASE SUSPEND & RESUME

The device allows the interruption of Sector Erase, Block Erase, or Page Program operations to conduct other

operations. 75h/B0h command for suspend and 7Ah/30h for resume will be used. (SPI/QPI all acceptable) Function

Suspend to read ready timing (tSUS): 100µs (MAX)

Resume to another suspend timing (tRS): 80µs (TYP)

SUSPEND DURING SECTOR-ERASE OR BLOCK-ERASE (PERSUS 75h/B0h)

The Suspend command allows the interruption of Sector Erase and Block Erase operations. But Suspend command

will be ignored during Chip Erase operation. After the Suspend command, other commands include array read

operation can be accepted.

But all non-volatile register write instructions including Write Status Register command (01h) and Erase instructions

are not allowed during Erase Suspend. Also, array read for being erased sector/block is not allowed.

To execute Erase Suspend operation, the host drives CE# low, sends the Suspend command cycle (75h/B0h),

then drives CE# high. The Function Register indicates that the Erase has been suspended by setting the ESUS bit

from “0” to “1”, but the device will not accept another command until it is ready. To determine when the device will

accept a new command, poll the WIP bit or wait the specified time tSUS. When ESUS bit is set to “1”, the Write

Enable Latch (WEL) bit clears to “0”.

SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)

The Suspend command also allows the interruption of all array Program operations. After the Suspend command,

other commands include array read operation can be accepted.

But all non-volatile register write instructions including Write Status Register instruction (01h) and Program

instructions are not allowed during Program Suspend. Also, array read for being programmed page is not allowed.

To execute the Program Suspend operation, the host drives CE# low, sends the Suspend command cycle

(75h/B0h), then drives CE# high. The Function Register indicates that the programming has been suspended by

setting the PSUS bit from “0” to “1”, but the device will not accept another command until it is ready. To determine

when the device will accept a new command, poll the WIP bit or wait the specified time tSUS. When PSUS bit is set

to “1”, the Write Enable Latch (WEL) bit clears to “0”.

PROGRAM/ERASE RESUME (PERRSM 7Ah/30h)

The Program/Erase Resume restarts the Program or Erase command that was suspended, and clears the suspend

status bit in the Function Register (ESUS or PSUS bits) to “0”. To execute the Program/Erase Resume operation,

the host drives CE# low, sends the Program/Erase Resume command cycle (7Ah/30h), then drives CE# high. A

cycle is two nibbles long, most significant nibble first. To issue another Erase Suspend operation after Erase

Resume operation, Erase Resume to another Erase Suspend delay (tRS) is required.

To determine if the internal, self-timed Write operation completed, poll the WIP bit.

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