IS25LE02GG-RHLA2:P-TY datasheet(63/187 Pages) ISSI

部件名	IS25LE02GG-RHLA2:P-TY

功能描述	SERIAL FLASH MEMORY 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	187 Pages

Scroll/Zoom	100%

制造商	ISSI [Integrated Silicon Solution, Inc]

网页	http://www.issi.com

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63 / 187 page

IS25LE02GG

IS25WE02GG

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A1

10/02/2025

Figure 8.6 Fast Read Sequence In QPI Mode (0Bh [EXTADD=1] or 0Ch, 4-byte address)

0Bh/0Ch

CE#

SCK

IO[3:0]

6 Dummy Cycles

4-byte Address

...

Mode 3

Mode 0

31:28

7:4

3:0

Data 1

27:24

15:12 11:8

7:4

3:0

...

Instruction

23:20 19:16

Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy

Cycles.

8.5 HOLD OPERATION

HOLD# is used in conjunction with CE# to select the device. When the device is selected and a serial sequence is

underway, HOLD# can be used to pause the serial communication with the master device without resetting the

serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication,

HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to SI will be ignored

while SO is in the high impedance state, during HOLD.

Note: HOLD is not supported in DTR mode or with QE=1 or when RESET# is selected for the HOLD# or RESET# pin.

Timing graph can be referenced in AC Parameters Figure 9.4.

IS25LE02GG-RHLA2:P-TY 数据表(PDF) 63 Page - Integrated Silicon Solution, Inc

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