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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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IS25LE02GG-RHLA2:P-TY 数据表(PDF) 28 Page - Integrated Silicon Solution, Inc |
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IS25LE02GG-RHLA2:P-TY 数据表(HTML) 28 Page - Integrated Silicon Solution, Inc |
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28 / 187 page  IS25LE02GG IS25WE02GG Integrated Silicon Solution, Inc.- www.issi.com 28 Rev. A1 10/02/2025 Table 6.10 Wrap Function Wrap around boundary P2 Whole array regardless of P1 and P0 value 0 Burst Length set by P1 and P0 1 Table 6.11 Read Dummy Cycles vs Max Frequency P[6:3] Dummy Cycles2,3 Fast Read5 0Bh/0Ch Fast Read Dual Output 3Bh/3Ch Fast Read Dual IO BBh/BCh Fast Read Quad Output 6Bh/6Ch Fast Read Quad IO EBh/ECh FRDTR 0Dh/0Eh FRDDTR BDh/BEh FRQDTR EDh/EEh SPI QPI SPI SPI SPI SPI, QPI SPI/QPI SPI4 SPI, QPI 0 Default1 133MHz 70MHz 120MHz 60MHz 104MHz 60MHz 66/55MHz 40MHz 55MHz 1 1 80MHz 20MHz 65MHz 45MHz 50MHz 20MHz 20/5MHz 15MHz 5MHz 2 2 85MHz 30MHz 70MHz 50MHz 55MHz 25MHz 25/15MHz 20MHz 15MHz 3 3 90MHz 40MHz 75MHz 55MHz 60MHz 30MHz 30/25MHz 30MHz 25MHz 4 4 95MHz 50MHz 85MHz 60MHz 65MHz 40MHz 35/35MHz 40MHz 35MHz 5 5 100MHz 60MHz 95MHz 70MHz 70MHz 50MHz 40/45MHz 50MHz 45MHz 6 6 110MHz 70MHz 100MHz 80MHz 80MHz 60MHz 50/55MHz 60MHz 55MHz 7 7 120MHz 75MHz 110MHz 90MHz 90MHz 70MHz 60/60MHz 66MHz 60MHz 8 8 133MHz 85MHz 120MHz 100MHz 104MHz 80MHz 66/66MHz 66MHz 66MHz 9 9 133MHz 95MHz 125MHz 110MHz 110MHz 90MHz 66/66MHz 66MHz 66MHz 10 10 133MHz 104MHz 130MHz 120MHz 120MHz 100MHz 66/66MHz 66MHz 66MHz 11 11 133MHz 114MHz 133MHz 130MHz 130MHz 110MHz 66/66MHz 66MHz 66MHz 12 12 133MHz 124MHz 133MHz 133MHz 133MHz 120MHz 66/66MHz 66MHz 66MHz 13 13 133MHz 133MHz 133MHz 133MHz 133MHz 130MHz 66/66MHz 66MHz 66MHz 14 14 133MHz 133MHz 133MHz 133MHz 133MHz 133MHz 66/66MHz 66MHz 66MHz 15 15 133MHz 133MHz 133MHz 133MHz 133MHz 133MHz 66/66MHz 66MHz 66MHz Notes: 1. Default dummy cycles are as follows. Operation Command Dummy Cycles Comment SPI mode QPI mode SPI mode QPI mode Fast Read 0Bh/0Ch 0Bh/0Ch 8 6 RDUID, IRRD operations are also applied. Fast Read Dual Output 3Bh/3Ch - 8 - Fast Read Quad Output 6Bh/6Ch - 8 - Fast Read Dual IO BBh/BCh - 4 - Fast Read Quad IO EBh/ECh EBh/ECh 6 6 Fast Read DTR 0Dh/0Eh 0Dh/0Eh 8 6 Fast Read Dual IO DTR BDh/BEh - 4 - Fast Read Quad IO DTR EDh/EEh EDh/EEh 6 6 2. Enough number of dummy cycles must be applied to execute properly the AX read operation. 3. Must satisfy bus I/O contention. For instance, if the number of dummy cycles and AX bits cycles are same, then X must be Hi-Z. 4. QPI mode is not available for FRDDTR command. 5. RDUID, IRRD instructions are also applied. |
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