IS25LE02GG-RHLA2:P-TY datasheet(12/187 Pages) ISSI

12 / 187 page

IS25LE02GG

IS25WE02GG

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A1

10/02/2025

4. SPI MODES DESCRIPTION

Multiple IS25LE02GG devices or multiple IS25WE02GG devices can be connected on the SPI serial bus and

controlled by a SPI Master, i.e. microcontroller, as shown in Figure 4.1. The devices support either of two SPI

modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the serial

clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure

4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge of Serial Clock

(SCK), and the output data is available from the falling edge of SCK.

Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

SPI interface with

(0,0) or (1,1)

SPI Master

(i.e. Microcontroller)

SPI

Memory

Device

SPI

Memory

Device

SPI

Memory

Device

SCK SO

SCK

SDI

SDO

CE#

WP#

SCK SO

CE#

WP#

SCK SO

CE#

WP# HOLD#

or RESET#

CS3

CS2

CS1

HOLD#

or RESET#

HOLD#

or RESET#

Notes:

1. In case of 16-pin SOIC and 24-ball TFBGA, dedicated RESET# is supported.

2. SI and SO pins become bidirectional IO0 and IO1 respectively during Dual I/O mode and SI, SO, WP#, and HOLD#

pins become bidirectional IO0, IO1, IO2, and IO3 respectively during Quad I/O or QPI mode.

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