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IS25LE02GG-RHLA2:P-TY 数据表(PDF) 173 Page - Integrated Silicon Solution, Inc

部件名 IS25LE02GG-RHLA2:P-TY
功能描述  SERIAL FLASH MEMORY 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  187 Pages
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制造商  ISSI [Integrated Silicon Solution, Inc]
网页  http://www.issi.com
标志 ISSI - Integrated Silicon Solution, Inc

IS25LE02GG-RHLA2:P-TY 数据表(HTML) 173 Page - Integrated Silicon Solution, Inc

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IS25LE02GG
IS25WE02GG
Integrated Silicon Solution, Inc.- www.issi.com
173
Rev. A1
10/02/2025
8.71 READ ECC REGISTER OPERATION (RDECC, B3h)
The Read ECC Register (RDECC) instruction provides access to the ECC Register. The instruction is shifted on
SI, then the 48-bit ECC Register data is shifted out on SO from bit 7 of 1st byte.
Register data is coming out continuously until CE# goes High. 1st byte data is coming out again after 6th byte data
when CE# remains Low.
Note: 2Gb is an MCP of four 512Mb die, so the ECC register data after RDECC command is from one die
(previously selected die), and additional dummy read from another die (to select another die) + RDECC
command is required to get ECC register data from another die. RDECC operation is preformed per
individual die. RDECC operation is performed per each 512Mb die.
Figure 8.156 Read ECC Register Sequence In SPI Mode
Instruction = B3h
CE#
SCK
SI
SO
0
1
...
7
8
9
...
15
16
17
...
23
...
64
48
...
Mode 3
Mode 0
tV
7
15
14
8
6
...
0
47
46
40
...
...
...
55
1st byte Data Out
2nd byte Data Out
...
6th byte Data Out
Figure 8.157 Read ECC Register In QPI Mode
B3h
CE#
SCK
IO[3:0]
0
1
Mode 3
Mode 0
2
3
4
5
7:0
15:8
...
47:40
...
12
13
1st byte
Data Out
2nd byte
Data Out
6th byte
Data Out



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