STM32H533CE datasheet(34/231 Pages) STMICROELECTRONICS

34 / 231 page

Functional overview

STM32H533xx

34/231

DS14539 Rev 1

•

Per channel event generation, on any of the following events: transfer complete or half

transfer complete or data transfer error or user setting error, and/or update linked-list

item error or completed suspension

•

Per channel interrupt generation, with separately programmed interrupt enable per

event

•

8 concurrent DMA channels:

–

Per channel FIFO for queuing source and destination transfers

–

Intra-channel DMA transfers chaining via programmable linked-list into memory,

supporting two execution modes: run-to-completion and link step mode

–

Intra-channel and inter-channel DMA transfers chaining via programmable DMA

input triggers connection to DMA task completion events

•

Per linked-list item within a channel:

–

Separately programmed source and destination transfers

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Programmable data handling between source and destination: byte-based

reordering, packing or unpacking, padding or truncation, sign extension and

left/right realignment

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Programmable number of data bytes to be transferred from the source, defining

the block level

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6 channels with linear source and destination addressing: either fixed or

contiguously incremented addressing, programmed at a block level, between

successive single transfers

–

Four channels with 2D source and destination addressing: programmable signed

address offsets between successive burst transfers (non-contiguous addressing

within a block, combined with programmable signed address offsets between

successive blocks, at a second 2D/repeated block level)

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Support for scatter-gather (multi-buffer transfers), data interleaving and

de-interleaving via 2D addressing

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Programmable DMA request and trigger selection

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Programmable DMA half-transfer and transfer complete events generation

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Pointer to the next linked-list item and its data structure in memory, with automatic

update of the DMA linked-list control registers

•

Debug:

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Channel suspend and resume support

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Channel status reporting including FIFO level and event flags

•

TrustZone support:

–

Support for secure and non-secure DMA transfers, independently at a first

channel level, and independently at a source/destination and link sub-levels

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Secure and non-secure interrupts reporting, resulting from any of the respectively

secure and non-secure channels

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TrustZone-aware AHB slave port, protecting any DMA secure resource (register,

•

Privileged/unprivileged support:

–

Support for privileged and unprivileged DMA transfers, independently at a channel

level

–

Privileged-aware AHB slave port

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