CC2564MODACMOG datasheet(39/68 Pages) TI2

39 / 68 page

CC2564MODN, CC2564MODA

www.ti.com

SWRS160E – FEBRUARY 2014 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

6.2.1.4.2 Ground

The common ground must be the solid ground plane in Layer 2. TI recommends using a large ground pad

under and around the module and placing enough ground vias beneath for a stable system and thermal

dissipation (see Figure 6-11).

Figure 6-11. Using a Large Ground Pad Under the Module

6.2.1.5

Clock Guidelines

Remember that clock signal routing directly influences RF performance because of the signal trace

susceptibility to noise.

6.2.1.5.1 Slow Clock

TI recommends the following guidelines:

•

Keep the slow clock signal lines as short as possible and at least 4-mils wide.

•

Traces of slow clock signals must have a ground plane on each side of the signal trace to reduce

undesired signal coupling.

•

To reduce the capacitive coupling of undesired signals into the clock line, do not route slow clock

traces above or below other signals (especially digital signals). Figure 6-12 shows the slow clock trace

in the TI reference design.

CC2564MODACMOG 数据表(PDF) 39 Page - Texas Instruments