数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CC2564MODACMOG 数据表(PDF) 13 Page - Texas Instruments

部件名 CC2564MODACMOG
功能描述  CC2564MODx Bluetooth® Host Controller Interface (HCI) Module
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

CC2564MODACMOG 数据表(HTML) 13 Page - Texas Instruments

Back Button CC2564MODACMOG Datasheet HTML 9Page - Texas Instruments CC2564MODACMOG Datasheet HTML 10Page - Texas Instruments CC2564MODACMOG Datasheet HTML 11Page - Texas Instruments CC2564MODACMOG Datasheet HTML 12Page - Texas Instruments CC2564MODACMOG Datasheet HTML 13Page - Texas Instruments CC2564MODACMOG Datasheet HTML 14Page - Texas Instruments CC2564MODACMOG Datasheet HTML 15Page - Texas Instruments CC2564MODACMOG Datasheet HTML 16Page - Texas Instruments CC2564MODACMOG Datasheet HTML 17Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 68 page
background image
10 bits
td_uart_swrs064
t1
HCI_RTS
Start bit
Stop bit
HCI_RX
HCI_CTS
HCI_TX
t3
t4
t6
t2
13
CC2564MODN, CC2564MODA
www.ti.com
SWRS160E – FEBRUARY 2014 – REVISED JANUARY 2017
Submit Documentation Feedback
Product Folder Links: CC2564MODN CC2564MODA
Specifications
Copyright © 2014–2017, Texas Instruments Incorporated
(1)
An internal 300-kΩ pulldown retains shut-down mode when no external signal is applied to this pin.
4.7.1.5
nSHUTD Requirements
Table 4-3. nSHUTD Requirements
PARAMETER
MIN
MAX
UNIT
VIH
Operation mode level (1)
1.42
1.98
V
VIL
Shutdown mode level (1)
0
0.4
V
Minimum time for nSHUT_DOWN low to reset the device
5
ms
tr and tf
Rise and fall times
20
µs
4.7.2
Clock Specifications
Table 4-4. Slow Clock Requirements
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
Input slow clock frequency
32768
Hz
Input slow clock accuracy
(Initial + temp + aging)
Bluetooth
±250
ppm
ANT
±50
tr and
tf
Input transition time tr and tf
(10% to 90%)
200
ns
Frequency input duty cycle
15%
50%
85%
VIH
Slow clock input voltage limits
Square wave, DC-coupled
0.65 ×
VDD_IO
VDD_IO
V peak
VIL
0
0.35 ×
VDD_IO
V peak
Input impedance
1
Input capacitance
5
pF
4.7.3
Peripherals
4.7.3.1
UART
Figure 4-2 shows the UART timing diagram.
Figure 4-2. UART Timing



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com