HCF1305-2R2-R datasheet(18/39 Pages) MICROCHIP

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MIC24054

DS20007043B-page 18

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2025-2026 Microchip Technology Inc. and its subsidiaries

4.4

VDD Regulator

The MIC24054 provides a 5V regulated output for input

voltage (VIN) ranging from 5.5V to 19V. When

VIN < 5.5V, VDD should be tied to the PVIN pins to

bypass the internal linear regulator.

4.5

Soft-Start

Soft-start reduces the power supply input surge current

at start-up by controlling the output voltage rise time.

The input surge appears while the output capacitor is

charged up. A slower output rise time draws a lower

input surge current.

The MIC24054 implements an internal digital soft-start

by making the 0.8V reference voltage (VREF) ramp

from 0% to 100% in about 3 ms with 9.7 mV steps.

Therefore, the output voltage is controlled to increase

slowly by a stair-case VFB ramp. Once the soft-start

cycle ends, the related circuitry is disabled to reduce

current consumption. VDD must be powered up at the

same time or after VIN to make the soft-start function

correctly.

4.6

Current Limit

The MIC24054 uses the RDS(ON) of the internal

low-side power MOSFET to sense overcurrent

conditions. This method avoids adding cost, board

space, and power losses taken by a discrete current

sense resistor. The low-side MOSFET is used because

it displays much lower parasitic oscillations during

switching than the high-side MOSFET.

In each switching cycle of the MIC24054 converter, the

inductor current is sensed by monitoring the low-side

MOSFET in the OFF period. If the inductor current is

greater than 14A, then the MIC24054 turns off the

high-side MOSFET and a soft-start sequence is

triggered. This mode of operation is called “hiccup

mode” and its purpose is to protect the downstream

load in case of a hard short. The load current-limit

threshold has a foldback characteristic related to the

feedback voltage as shown in Figure 4-4.

FIGURE 4-4:

Current-Limit Foldback

Characteristics.

4.7

Power Good (PG)

The Power Good (PG) pin is an open-drain output that

indicates logic-high when the output is nominally 92%

of its steady state voltage. A pull-up resistor of more

than 10 kΩ should be connected from PG to VDD.

4.8

MOSFET Gate Driver

The Functional Block Diagram shows a bootstrap

circuit, consisting of D1 (a Schottky diode is

recommended) and CBST. This circuit supplies energy

to the high-side drive circuit. Capacitor CBST is

charged, while the low-side MOSFET is on, and the

voltage on the SW pin is approximately 0V. When the

high-side MOSFET driver is turned on, energy from

CBST is used to turn the MOSFET on. As the high-side

MOSFET turns on, the voltage on the SW pin increases

to approximately VIN. Diode D1 is reverse-biased and

CBST floats high while continuing to keep the high-side

MOSFET on. The bias current of the high-side driver is

less than 10 mA, so a 0.1 μF to 1 μF is sufficient to hold

the gate voltage with minimal droop for the power

stroke (high-side switching) cycle (i.e. ΔBST = 10 mA x

1.67 μs/0.1 μF = 167 mV). When the low-side

MOSFET is turned back on, CBST is recharged through

D1. A small resistor RG, which is in series with CBST,

can be used to slow down the turn-on time of the

high-side N-channel MOSFET.

The drive voltage is derived from the VDD supply

voltage. The nominal low-side gate drive voltage is VDD

and the nominal high-side gate drive voltage is

approximately VDD – VDIODE, where VDIODE is the

voltage drop across D1. An approximate 30 ns delay

between the high-side and low-side driver transitions is

used to prevent current from simultaneously flowing

unimpeded through both MOSFETs.

0.0

0.2

0.4

0.6

0.8

1.0

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