HCF1305-2R2-R datasheet(24/39 Pages) MICROCHIP

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MIC24054

DS20007043B-page 24



2025-2026 Microchip Technology Inc. and its subsidiaries

6.0

PCB LAYOUT GUIDELINES

PCB layout is critical to achieve reliable, stable, and

efficient performance. A ground plane is required to

control EMI and minimize the inductance in power,

signal and return paths.

To minimize EMI and output noise, the following

guidelines should be followed to ensure proper

operation of the MIC24054.

6.1

• A 2.2 μF ceramic capacitor, which is connected to

the PVDD pin, must be located right at the IC. The

PVDD pin is very noise sensitive and placement

of the capacitor is very critical. Use wide traces to

connect to the PVDD and PGND pins.

• A 1 μF ceramic capacitor must be placed right

between VDD and the signal ground SGND. The

SGND pin must be connected directly to the

ground planes. Do not route the SGND pin to the

PGND Pad on the top layer.

• Place the IC close to the point-of-load (POL).

• Use wide traces to route the input and output

power lines.

• Signal and power grounds should be kept

separate and connected at only one location.

6.2

Input Capacitor

• Place the input capacitors on the same side of the

board and as close to the IC as possible.

• Keep both the PVIN pin and PGND connections

short.

• Place several vias to the ground plane close to

the input capacitor ground terminal.

• Use either X7R or X5R dielectric input capacitors.

Do not use Y5V or Z5U type capacitors.

• Do not replace the ceramic input capacitor with

any other type of capacitor. Any type of capacitor

can be placed in parallel with the input capacitor.

• If a Tantalum input capacitor is placed in parallel

with the input capacitor, it must be recommended

for switching regulator applications and the

operating voltage must be derated by 50%.

• In “Hot-Plug” applications, a Tantalum or

Electrolytic bypass capacitor must be used to limit

the overvoltage spike seen on the input supply

with power is suddenly applied.

6.3

Inductor

• Keep the inductor connection to the switch node

(SW) short.

• Do not route any digital lines underneath or close

to the inductor.

• Keep the switch node (SW) away from the

feedback (FB) pin.

• The CS pin should be connected directly to the

SW pin to accurate sense the voltage across the

low-side MOSFET.

• To minimize noise, place a ground plane

underneath the inductor.

• The inductor can be placed on the opposite side

of the PCB with respect to the IC. It does not

matter whether the IC or inductor is on the top or

bottom as long as there is enough air flow to keep

the power components within their temperature

limits. The input and output capacitors must be

placed on the same side of the board as the IC.

6.4

Output Capacitor

• Use a wide trace to connect the output capacitor

ground terminal to the input capacitor ground

terminal.

• Phase margin will change as the output capacitor

value and ESR changes. Contact the factory if the

output capacitor is different from what is shown in

the BOM.

• The feedback trace should be separate from the

power trace and connected as close as possible

to the output capacitor. Sensing a long high

current load trace can degrade the DC load

regulation.

6.5

Optional RC Snubber

• Place the RC snubber on either side of the board

and as close to the SW pin as possible.

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