HCF1305-2R2-R datasheet(15/39 Pages) MICROCHIP

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DS20007043B-page 15

MIC24054

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Number

Pin Name

Description

PVDD

5V Internal Linear Regulator output. PVDD supply is the power MOSFET gate drive

supply voltage and created by internal LDO from VIN. When VIN < +5.5V, PVDD

should be tied to the PVIN pins. A 2.2 µF ceramic capacitor from the PVDD pin to

PGND (Pin 2) must be placed next to the IC.

2, 5, 6, 7, 8, 21

PGND

Power Ground. PGND is the ground path for the MIC24054 buck converter power

stage. The PGND pins connect to the source of the low-side N-channel MOSFET,

gate driver supply ground of the low-side N-channel MOSFET, the negative

terminals of input capacitors, and the negative terminals of output capacitors. The

loop for the power ground should be as small as possible and separate from the

signal ground (SGND) loop.

No connect.

4, 9, 10, 11, 12

Switch Node output. Internal connection for the high-side MOSFET source and

low-side MOSFET drain. Due to the high speed switching on this pin, the SW pin

should be routed away from sensitive nodes.

13,14,15,

16,17,18,19

PVIN

High-Side N-internal MOSFET Drain Connection input. The PVIN operating voltage

range is from 4.5V to 19V. Input capacitors between the PVIN pins and the power

ground (PGND) are required and keep the connection short.

BST

Bootstrap output. Bootstrapped voltage to the high-side N-channel MOSFET driver.

A Schottky diode is connected between the PVDD pin and the BST pin. A boost

capacitor of 0.1 μF is connected between the BST pin and the SW pin. Adding a

small resistor at the BST pin can slow down the turn-on time of high-side N-Channel

MOSFETs.

Current Sense input. The CS pin senses current by monitoring the voltage across

the low-side MOSFET during the OFF-time. The current sensing is necessary for

short-circuit protection and zero current cross comparator. In order to sense the

current accurately, connect the low-side MOSFET drain to SW using a Kelvin

connection. The CS pin is also the high-side MOSFET’s output driver return.

SGND

Signal Ground. SGND must be connected directly to the ground planes. Do not route

the SGND pin to the PGND pad on the top layer, see PCB layout guidelines for

details.

Feedback input. Input to the transconductance amplifier of the control loop. The FB

pin is regulated to 0.8V. A resistor divider connecting the feedback to the output is

used to adjust the desired output voltage.

Power Good output. Open drain output. The PG pin is externally tied with a resistor

to VDD. A high output is asserted when VOUT > 92% of nominal.

Enable input. A logic level control of the output. The EN pin is CMOS-compatible.

Logic high = enable, logic low = shutdown. In the off state, supply current of the

device is greatly reduced (typically 5 µA). The EN pin should not be left floating.

VIN

Power Supply Voltage input. Requires bypass capacitor to SGND.

VDD

5V Internal Linear Regulator output. VDD supply is the supply bus for the IC control

circuit. VDD is created by internal LDO from VIN. When VIN < +5.5V, VDD should be

tied to the PVIN pins. A 1 µF ceramic capacitor from the VDD pin to the SGND pin

must be place next to the IC.

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