AD8510/AD8512/AD8513

Rev. H | Page 15 of 20

Figure 46 shows a scope plot of the output of the AD8510/AD8512/

AD8513 in response to a 400 mV pulse. The circuit is configured in

positive unity gain (worst case) with a load experience of 500 pF.

TIME (1µs/DIV)

Figure 46. Capacitive Load Drive Without Snubber

When the snubber circuit is used, the overshoot is reduced from

55% to less than 3% with the same load capacitance. Ringing is

virtually eliminated, as shown in Figure 47.

TIME (1µs/DIV)

Figure 47. Capacitive Load with Snubber Network

and input stray capacitance and are determined empirically.

Table 5 shows a few values that can be used as starting points.

Table 5. Optimum Values for Capacitive Loads

500 pF

100

1 nF

2 nF

70

100 pF

5 nF

60

300 pF

OPEN-LOOP GAIN AND PHASE RESPONSE

In addition to their impressive low noise, low offset voltage, and

offset current, the AD8510/AD8512/AD8513 have excellent

loop gain and phase response even when driving large resistive

and capacitive loads.

Compared with Competitor A (see Figure 49) under the same

conditions, with a 2.5 kΩ load at the output, the AD8510/AD8512/

AD8513 have more than 8 MHz of bandwidth and a phase margin

of more than 52°.

Competitor A, on the other hand, has only 4.5 MHz of band-

width and 28° of phase margin under the same test conditions.

Even with a 1 nF capacitive load in parallel with the 2 kΩ load

at the output, the AD8510/AD8512/AD8513 show much better

response than Competitor A, whose phase margin is degraded

to less than 0, indicating oscillation.

FREQUENCY (Hz)

10k

–30

–20

–10

100k

0

10

30

1M

10M

50M

40

50

20

60

70

–135

–90

–45

0

45

90

135

180

225

270

315

Figure 48. Frequency Response of the AD8510/AD8512/AD8513

FREQUENCY (Hz)

10k

–30

–20

–10

100k

0

10

30

1M

10M

50M

40

50

20

60

70

–135

–90

–45

0

45

90

135

180

225

270

315

Figure 49. Frequency Response of Competitor A