MSB7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

SCK

EN

CSN

CSN

SCK

SDI

SDO

td

SDI

CURRENT B

POLARITY B

POLARITY A

D99AT437

MSB7

bit6

bit7

bit7

bit5

bit4

bit3

bit2

bit1

bit0

bit0

bit0

SDO

AX

CURRENT A

ERROR BITS

Figure 7. SPI Data/Clock Timing.

Serial Data Interface (SPI)

The serial data interface itself consists of the pins SCL (serial clock), SDI (serial data input) and SDO

(serial data output).

To especially support bus controlled applications the additional signals EN (chip enable not) and CSN

(chip select not) are available.

Startup of the Serial Data Interface

Falling slope of CSN indicates start of frame. Data transfer (reading SDI into the register) takes place at

the rising slopes of SCK.

Data transfer of the register to SDO takes place at the falling slope of SCK.

Rising slope of CSN indicates end of frame. At the end of frame data will only be accepted if modulo 8

bit (modulo 8 falling slopes to SCK) have been transferred. If this is not the case the input will be ignored

and the bridges will maintain the same status as before.

SDO is a tristate output.

SDO is active while CSN = LOW, while CSN = HIGH SDO is high resistive.

L9935

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