M14C64, M14C32

8/14

Random Address Read

A dummy write is performed to load the address

into the address counter, as shown in Figure 9.

This is followed by another START condition from

the master and the device select is repeated with

the RW bit set to ‘1’. The memory acknowledges

this, and outputs the byte addressed. The master

must

nates the transfer with a STOP condition.

Sequential Read

This mode can be initiated with either a Current

Address Read or a Random Address Read. How-

ever, in this case the master

Current Address Read

The memory has an internal address counter.

Each time a byte is read, this counter is increment-

ed. For the Current Address Read mode, following

a START condition, the master sends a device se-

lect with the RW bit set to ‘1’. The memory ac-

knowledges this, and outputs the byte addressed

by the internal address counter. The counter is

then incremented. The master must

edge the byte output, and terminates the transfer

with a STOP condition, as shown in Figure 9.

Figure 9. Read Mode Sequences

DEV SEL *

BYTE ADDR

BYTE ADDR

DEV SEL

DATA OUT 1

AI01105C

DATA OUT N

CURRENT

ADDRESS

READ

DEV SEL

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

DATA OUT

SEQUENTIAL

CURRENT

READ

DATA OUT N

DEV SEL *

BYTE ADDR

BYTE ADDR

SEQUENTIAL

RANDOM

READ

DEV SEL *

DATA OUT 1

ACK

R/W

NO ACK

ACK

R/W

ACK

ACK

ACK

R/W

ACK

ACK

ACK

NO ACK

R/W

NO ACK

ACK

ACK

ACK

R/W

ACK

ACK

R/W

ACK

NO ACK