M14C64, M14C32

6/14

Figure 7. Write Mode Sequences with WC=0

BYTE WRITE

DEV SEL

BYTE ADDR

BYTE ADDR

DATA IN

WC

PAGE WRITE

DEV SEL

BYTE ADDR

BYTE ADDR

DATA IN 1

WC

DATA IN 2

AI01106B

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

R/W

ACK

ACK

ACK

ACK

ACK

ACK

ACK

R/W

ACK

ACK

Table 6. Operating Modes

Note: 1. X =

Mode

RW bit

Bytes

Initial Sequence

Current Address Read

‘1’

X

1

START, Device Select, RW = ‘1’

Random Address Read

‘0’

X

START, Device Select, RW = ‘0’, Address

‘1’

X

1

reSTART, Device Select, RW = ‘1’

Sequential Read

‘1’

X

≥ 1

Similar to Current or Random Mode

Byte Write

‘0’

1

START, Device Select, RW = ‘0’

Page Write

‘0’

≤ 32

START, Device Select, RW = ‘0’

Page Write

The Page Write mode allows up to 32 bytes to be

written in a single write cycle, provided that they

are all located in the same ’row’ in the memory:

that is the most significant memory address bits

(b13-b5 for the M14C64 and b12-b5 for the

M14C32) are the same. The master sends from

one up to 32 bytes of data, each of which is ac-

knowledged by the memory if the WC pin is low. If

the WC pin is high, each data byte is followed by a

NoACK and the location is not modified. After each

byte is transferred, the internal byte address coun-

ter (the five least significant bits only) is increment-