M25P10

8/21

Read Status Register (RDSR)

The RDSR instruction provides access to the

Status Register content. The Status Register may

be read at any time, even during a Page Program,

Sector Erase, Bulk Erase or Write Status Register.

When one of these instructions is in progress, it is

recommended to check the WIP bit before sending

a new instruction to the device. For this, it is

possible to continuously read the Status Register

value.

WIP bit: The Write-In-Process (WIP) bit indicates

whether the memory is busy with a Write Status

Register, Program or Erase operation. When set

to a ’1’, such an operation is in progress, when set

to a ’0’ no such operation is in progress.

WEL bit: The Write Enable Latch (WEL) bit

indicates the status of the internal Write Enable

Latch. When set to a ’1’ the latch is set, when set

to a ’0’ the latch is reset and no Write Status

Register, Program or Erase sequence will be

allowed.

BP1,BP0 bits: The Block Protect bits BPi are non-

volatile bits. They define the size of the area to be

software protected against Program and Erase

operations. These bits are written with the WRSR

instruction (see Table 5). Once (BP0, BP1) are set

to a value different from (0,0), the relevant area

becomes protected against Page Program and

Sector Erase operations. BPi bits can be written

provided that the Hardware Protected Mode has

not been set. The Bulk Erase instruction is

Figure 10. WRSR: Write Status Register Sequence

C

D

AI02282

S

Q

2

1

3456789 10 11 12 13 14 15

HIGH IMPEDANCE

INSTRUCTION

STATUS REG.

0

765432

0

1

MSB

Figure 11. READ: Read Data Bytes Sequence

Note: 1. Address bits A23 to A17 are Don’t Care on the M25P10 series.

C

D

AI03748

S

Q

23

2

1

3456789 10

28 29 30 31 32 33 34 35

22 21

3210

36 37 38

765432

0

1

HIGH IMPEDANCE

DATA OUT

INSTRUCTION

24 BIT ADDRESS

0

MSB