M25P10

11/21

sets the Write Enable Latch (WEL) which allows

the execution of any further Bulk Erase. The Bulk

Erase instruction is entered by driving the Chip

select input (S) low, followed by the instruction

byte on Data In input (D).

The Chip Select input (S) must be driven low for

the entire duration of the sequence. The device

must be deselected just after the eighth bit of the

instruction byte has been latched in. If not, the

Bulk Erase instruction is not executed. As soon as

the device is deselected, the self-timed Bulk Erase

is in progress, the status register may be read to

check the WIP bit value. WIP is high during the

self-timed Bulk Erase cycle and is low when it is

completed. When the cycle is completed, the write

enable latch (WEL) is reset.

The Bulk Erase instruction is internally taken into

account if, and only if, (BP0, BP1) = (0,0). In other

words, the Bulk Erase instruction is ignored if at

least one Sector is software protected. In this case

the Bulk Erase instruction is discarded and none of

the Sectors are erased.

The timing sequence is shown in Figure 14.

Enter Deep Power Down Mode (DP)

After Power-on, when S is high, the memory is

deselected, the Q output pin is at high impedance

and the device is in the Standby Power Mode state

select condition and is able to receive, decode and

execute all instructions.This mode is not the Deep

Power Down Mode which is entered by the way of

a specific instruction. The purpose of the Deep

Power down mode is to drastically reduce the

Once the device has entered the Deep Power

Down Mode, all instructions are ignored except the

RES instruction which releases the part from this

Figure 15. DP: Enter Deep Power Down Mode Sequence

C

D

AI03753

S

2

1

34567

0

tDP

Deep Power Down Mode

Stand-by Power Down Mode

INSTRUCTION

Figure 16. RES: Release from Deep Power Down Mode and Read Electronic Signature Sequence

C

D

AI03755

S

Q

23

2

1

3456789 10

28 29 30 31 32 33 34 35

22 21

3210

36 37 38

765432

0

1

HIGH IMPEDANCE

DATA OUT (Electronic Signature)

INSTRUCTION

24 BIT ADDRESS

0

MSB

Stand-by Power Down Mode

Deep Power Down Mode