M28F201 datasheet(7/21 Pages) STMICROELECTRONICS

7 / 21 page

Symbol

Alt

Parameter

Test Condition

M28F201

Unit

-70

-90

-120

-150

VCC =

±10%

VCC =

±10%

VCC =

±10%

VCC =

±10%

EPROM

Interface

EPROM

Interface

EPROM

Interface

EPROM

Interface

Min

Max

Min

Max

Min

Max

Min

Max

tWHGL

Write Enable High to

Output Enable Low

6666

µs

tAVAV

tRC

Read Cycle Time

E = VIL,G = VIL

120

150

tAVQV

tACC

Address Valid to

Output Valid

E=VIL,G = VIL

120

150

tELQX

(1)

tLZ

Chip Enable Low to

Output Transition

G= VIL

0000

tELQV

tCE

Chip Enable Low to

Output Valid

G= VIL

120

150

tGLQX

(1 )

tOLZ

Output Enable Low

to Output Transition

E= VIL

0000

tGLQV

tOE

Output Enable Low

to Output Valid

E= VIL

tEHQZ

(1 )

Chip Enable High to

Output Hi-Z

G= VIL

tGHQZ

(1)

tDF

Output Enable High

to Output Hi-Z

E= VIL

tAXQX

tOH

Address Transition

to Output Transition

E=VIL,G = VIL

0000

Note: 1. Sampled only, not 100% tested

Table 9. Read Only Mode AC Characteristics

((TA = 0 to 70

°C, –40 to 85 °C or –40 to 125 °C)

Erase and Erase Verify Modes. The memory is

erased by first Programming all bytes to 00h, the

Erase command then erases them to FFh. The

Erase Verify command is then used to read the

memory byte-by-byte for a content of FFh. The

Erase Mode is set-up by writing 20h to the com-

mand register. The write cycle is then repeated to

start the erase operation. Erasure starts on the

rising edge of W during this second cycle. Erase is

followed by an Erase Verify which reads an ad-

dressed byte. Erase Verify Mode is set-up by writ-

ing A0h to the command register and at the same

time supplying the address of the byte to be veri-

fied. The rising edge of W during the set-up of the

first Erase Verify Mode stops the Erase operation.

The following read cycle is made with an internally

generated margin voltage applied; reading FFh

indicates that all bits of the addressed byte are fully

erased. The whole contents of the memory are

verified by repeating the Erase Verify Operation,

first writing the set-up code A0h with the address

of the byte to be verified and then reading the byte

contents in a second read cycle.

As the Erase algorithm flow chart shows, when the

data read during Erase Verify is not FFh, another

Erase operation is performed and verification con-

tinues from the address of the last verified byte. The

command is terminated by writing another valid

command to the command register (for example

Program or Reset).

7/21

M28F201

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