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M28F201 数据表(PDF) 16 Page - STMicroelectronics

部件名 M28F201
功能描述  2 Mb 256K x 8, Chip Erase FLASH MEMORY
PDF  21 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M28F201 数据表(HTML) 16 Page - STMicroelectronics

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PRESTO F ERASE ALGORITHM
The PRESTO F Erase Algorithm guarantees that
the device will be erased in a reliable way. The
algorithm first programs all bytes to 00h in order to
ensure uniform erasure. The programming follows
the PRESTO F Programming Algorithm. Erase is
set-up by writing 20h to the command register, the
erasure is started by repeating this write cycle.
Erase Verify is set-up by writing A0h to the com-
mand register together with the address of the byte
to be verified. The subsequent read cycle reads the
data which is compared to FFh. Erase Verify begins
at address 0000h and continues to the last address
or until the comparison of the data to FFh fails. If
this occurs, the address of the last byte checked is
stored and a new Erase operation performed.
Erase Verify then continues from the address of the
stored location.
PRESTO F PROGRAM ALGORITHM
The PRESTO F Programming Algorithm applies a
series of 10
µs programming pulses to a byte until
a correct verify occurs. Up to 25 programming
operations are allowed for one byte. Program is
set-up by writing 40h to the command register, the
programming is started after the next write cycle
which also latches the address and data to be
programmed. Program Verify is set-up by writing
C0h to the command register, followed by a read
cycle and a compare of the data read to the data
expected. During Program and Program Verify op-
erations a MARGIN MODE circuit is activated to
guarantee that the cell is programmed with a safety
margin.
PROGRAM ALL
BYTES TO 00h
AI00649
n=0, Addr=00000h
Last
Addr
ERASE SET-UP
Wait 10ms
ERASE VERIFY
Latch Addr.
READ DATA OUTPUT
Data
OK
Wait 6
µs
++n
=
Addr++
READ COMMAND
VPP = 12V
VPP < 6.5V
FAIL
VPP < 6.5V, PASS
YES
NO
YES
NO
YES
NO
1000
Figure 12. Erasing Flowchart
AI00677
n= 0
Last
Addr
PROGRAM VERIFY
Wait 10
µs
PROGRAM SET-UP
Latch Addr, Data
READ DATA OUTPUT
Data
OK
Wait 6
µs
++n
=25
Addr++
READ COMMAND
VPP = 12V
VPP < 6.5V
FAIL
VPP < 6.5V, PASS
YES
NO
YES
NO
YES
NO
Figure 13. Programming Flowchart
16/21
M28F201



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