APM32E103CEU6-R datasheet(25/79 Pages) GEEHY

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Region

Start Address

Peripheral Name

AHB bus

0x0002 4400

Reserved

AHB bus

0x6000 0000

EMMC bank 1 NOR/PSRAM 1/SDRAM

AHB bus

0x6400 0000

EMMC bank 1 NOR/PSRAM 2/SDRAM

AHB bus

0x6800 0000

EMMC bank 1 NOR/PSRAM 3/SDRAM

AHB bus

0x6C00 0000

EMMC bank 1 NOR/PSRAM 4/SDRAM

AHB bus

0x7000 0000

EMMC bank 2 NAND(NAND1)

AHB bus

0x8000 0000

EMMC bank 3 NAND(NAND2)

AHB bus

0x9000 0000

EMMC bank 4 PCCARD

AHB bus

0xA000 0000

EMMC Register

—

0xA000 1000

Reserved

Core

0xE000 0000

M3 Core peripheral

Note: SDRAM is directly addressed to 256M, without Bank access separately.

4.1.3.

Startup configuration

At startup, the user can select one of the following three startup modes by setting the high and

low levels of the Boot pin:

⚫

Startup from main memory

⚫

Startup from BootLoader

⚫

Startup from built-in SRAM

The user can use USART interface to reprogram the user Flash if boot from BootLoader.

4.2.

Core

The core of APM32E103xCxE is Arm® Cortex®-M3. Based on this platform, the development

cost is low and the power consumption is low. It can provide excellent computing performance

and advanced system interrupt response, and is compatible with all Arm tools and software.

4.3.

Interrupt controller

4.3.1.

Nested Vector Interrupt Controller (NVIC)

It embeds a nested vectored interrupt controller (NVIC) that can handle up to 65 maskable

interrupt channels (not including 16 interrupt lines of Cortex®-M3) and 16 priority levels. The

interrupt vector entry address can be directly transmitted to the core, so that the interrupt

response processing with low delay can give priority to the late higher priority interrupt.

4.3.2.

External Interrupt/Event Controller (EINT)

The external interrupt/event controller consists of 19 edge detectors, and each detector

includes edge detection circuit and interrupt/event request generation circuit; each detector can

be configured as rising edge trigger, falling edge trigger or both and can be masked

independently. Up to 112 GPIOs can be connected to the 16 external interrupt lines.

4.4.

On-chip memory

On-chip memory includes main memory area, SRAM and information block; the information

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