APM32E103CEU6-R datasheet(27/79 Pages) GEEHY

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Figure 7 APM32E103xCxE Clock Tree

LSICLK

40KHz

LSECLK

OSC

32.768

KHz

4-16MHz

HSECLK

OSC

8MHz

HSICLK

/128

PLLHSEPSC PLLSEL

×2.3.4

...16

PLL

AHB

Prescaler

/1,2...512

APB1

Prescaler

/1,2,4,8,16

APB2

Prescaler

/1,2,4,8,16

CSS

RTC

IWDTCLK

FMCCLK

USBDCLK

SCSEL

TMR2,3,4,5,6,7

if(APB1 prescaler=1)×1

else×2

TMRxCLK

(x=2,3.

..7)

USBD

Prescaler

/1,1.5,

2,2.5

PCLK2

TMRxCLK

(x=1,8)

SMCCLK

TMR1,8

if(APB2 prescaler=1)×1

else×2

ADC

Prescaler

/2,4,6,8

ADCCLK

HCLK

SDIOCLK

PCLK1

FCLK

Cortex

System

Clock

PLLCLK

HSICLK

HSECLK

SYSCLK

MCO

I2SxCLK

(x=2,3)

RTCSEL[1:0]

HCLK/2

SYSCLK

120MHz

MAX

MCO

48MHz

120MHz MAX

60MHz MAX

FPUCLK

FPU

Prescaler

/1,2

120MHz MAX

60MHz MAX

OSC_OUT

OSC_IN

OSC32_OUT

OSC32_IN

DMCCLK

/1,2,4

4.5.1.

Clock source

Clock source is divided into high-speed clock and low-speed clock according to the speed; the

high-speed clock includes HSICLK and HSECLK, and the low-speed clock includes LSECLK

and LSICLK; clock source is divided into internal clock and external clock according to the chip

inside/outside; the internal clock includes HSICLK and LSICLK, and the external clock includes

HSECLK and LSECLK, among which HSICLK is calibrated by the factory to ±1% accuracy.

4.5.2.

System clock

HSICLK, PLLCLK and HSECLK can be selected as system clock; the clock source of PLLCLK

can be one of HSICLK and HSECLK; the required system clock can be obtained by configuring

PLL clock multiplier factor and frequency dividing coefficient.

When the product is reset and started, HSICLK is selected as the system clock by default, and

then the user can choose one of the above clock sources as the system clock by himself. When

HSECLK failure is detected, the system will automatically switch to the HSICLK, and if an

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