APM32E103CEU6-R datasheet(30/79 Pages) GEEHY

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USART mode/function

USART1

USART2

USART3

UART4

UART5

Single-line half-duplex mode

√

Support DMA function

√

—

Note: √ = support.

4.10.2.

I2C

I2C1/2 and I2C3 bus interfaces are built in. I2C1 and I2C3 share hardware interface and

I2C1/2 both can work in multiple master modes or slave modes, support 7-bit or 10-bit

addressing, and support dual-slave addressing in 7-bit slave mode; the communication rate

supports standard mode (up to 100kbit/s) and fast mode (up to 400kbit/s); hardware CRC

generator/checker are built in; they can operate with DMA and support SMBus 2.0

version/PMBus.

I2C3 bus can operate in standard mode, fast mode and high-speed mode. The devices in high-

speed mode and fast mode are downward compatible.

4.10.3.

SPI/I2S

Three built-in SPIs, support full duplex and half duplex communication in master mode and

slave mode, can use DMA controller, and can configure 4~16 bits per frame, and communicate

at a rate of up to 18Mbit/s.

2 built-in I2S (multiplexed with SPI2 and SPI3 respectively), support half duplex communication

in master mode and slave mode, support synchronous transmission, and can be configured

with 16-bit, 24-bit and 32-bit data transfer with 16-bit or 32-bit resolution. The configurable

range of audio sampling rate is 8kHz~48kHz; when one or two I2S interfaces are configured as

the master mode, the master clock can be output to external DAC or decoder (CODEC) at 256

times of sampling frequency.

4.10.4.

CAN

2 built-in CANs (CAN1 and CAN2 can be used at the same time), compatible with 2.0A and

2.0B (active) specification, and can communicate at a rate of up to 1Mbit/s. It can receive and

send standard frame of 11-bit identifier and extended frame of 29-bit identifier. It has 3 sending

mailboxes and 2 receiving FIFO, 28 3-level adjustable filters.

4.10.5.

USBD

The product embeds USBD modules (USBD1 and USBD2) compatible with full-speed USBD

devices, which comply with the standard of full-speed USBD devices (12Mb/s), and the

endpoints can be configured by software, and have standby/wake-up functions. The dedicated

48MHz clock for USBD is directly generated by internal PLL. When using the USBD function,

the system clock can only be one of 48MHz, 72MHz, 96MHz and 120MHz, which can obtain

48MHz required for USBD through 1 fractional frequency, 1.5 fractional frequency, 2 fractional

frequency and 2.5 fractional frequency respectively.

USBD1 and USBD2 share register address and pin interface, so only one of them can be used

at the same time.

4.10.6.

Simultaneous use of USBD and CAN interfaces

This product USBD1 (2) and CAN1 (2) sharing the same dedicated 512 - byte SRAM memory

used to send and receive data, USBD and CAN therefore be ready to use at the same

time.Details are as follows:

⚫

CAN1 and USBD2 could be used at the same time

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