STR71XF datasheet(68/78 Pages) STMICROELECTRONICS

68 / 78 page

Electrical parameters

STR71xF

68/78

Analog power supply and reference pins

The AVDD and AVSS pins are the analog power supply of the A/D converter cell. They act as

the high and low reference voltages for the conversion.

Separation of the digital and analog power pins allow board designers to improve A/D

performance. Conversion accuracy can be impacted by voltage drops and noise in the event

of heavily loaded or badly decoupled power supply lines (see: General PCB design

guidelines).

General PCB design guidelines

To obtain best results, some general design and layout rules should be followed when

designing the application PCB to shield the noise-sensitive, analog physical interface from

noise-generating CMOS logic signals.

●

Use separate digital and analog planes. The analog ground plane should be connected

to the digital ground plane via a single point on the PCB.

●

Filter power to the analog power planes. It is recommended to connect capacitors, with

good high frequency characteristics, between the power and ground lines, placing

0.1 µF and optionally, if needed 10 pF capacitors as close as possible to the STR7

power supply pins and a 1 to 10 µF capacitor close to the power source (see

Figure 39).

●

The analog and digital power supplies should be connected in a star network. Do not

use a resistor, as AVDD is used as a reference voltage by the A/D converter and any

resistance would cause a voltage drop and a loss of accuracy.

●

Properly place components and route the signal traces on the PCB to shield the analog

inputs. Analog signals paths should run over the analog ground plane and be as short

as possible. Isolate analog signals from digital signals that may switch while the analog

inputs are being sampled by the A/D converter. Do not toggle digital outputs near the

A/D input being converted.

Software filtering of spurious conversion results

For EMC performance reasons, it is recommended to filter A/D conversion outliers using

software filtering techniques.

Figure 39.

Power supply filtering

VSS

V33

0.1

µF

V33

STR710

AVDD

AVSS

POWER

SUPPLY

SOURCE

STR7

DIGITAL NOISE

FILTERING

EXTERNAL

NOISE

FILTERING

1 to 10

µF

0.1

µF

(3.3V)

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