STR71XF datasheet(24/78 Pages) STMICROELECTRONICS

24 / 78 page

System architecture

STR71xF

24/78

Table 7.

STR711/STR712/STR715 pin description

Pin n°

Pin name

Input

Output

Main

function

(after

reset)

Alternate function

1A1

P0.10/U1.RX/

U1.TX/

SC.DATA

I/O

CT X 4mA T

Port 0.10

UART1:

Receive Data

input

UART1: Transmit data

output.

Note: This pin may be used for

Smartcard DataIn/DataOut or single

wire UART (half duplex) if programmed

as Alternate Function Output. The pin

will be tri-stated except when UART

transmission is in progress

2B1

P0.11/BOOT.1

/U1.TX

I/O

4mA

Port 0.11

Select Boot

Configuration

input

UART1: Transmit data

output.

C1 P0.12/SC.CLK I/O

4mA

Port 0.12 Smartcard reference clock output

4B2 VSS

Ground voltage for digital I/Os2)

5C2

P0.13/U2.RX/

T2.OCMPA

I/O

CT X4mA X

Port 0.13

UART2:

Receive Data

input

Timer2: Output

Compare A output

6D1

P0.14/U2.TX/

T2.ICAPA

I/O

4mA

Port 0.14

UART2:

Transmit data

output

Timer2: Input Capture

A input

7C3 BOOTEN

Boot control input. Enables sampling of BOOT[1:0]

pins

8D2 VSS

Ground voltage for digital I/Os2)

9E1 V33

Supply voltage for digital I/Os2)

10 D3 JTDI

JTAG Data input. External pull-up required.

E2 JTMS

JTAG Mode Selection Input. External pull-up

required.

F1 JTCK

JTAG Clock Input. External pull-up or pull-down

required.

13 D4 JTDO

8mA

JTAG Data output. Note: Reset state = HiZ.

F2 JTRST

JTAG Reset Input. External pull-up required.

E3 NU

Reserved, must be forced to ground.

16 G1 TEST

Reserved, must be forced to ground.

17 H1 V33IO-PLL

Supply voltage for digital I/O circuitry and for PLL

reference2)

18 H2 VSSIO-PLL

Ground voltage for digital I/O circuitry and for PLL

reference2)

19 H3 CK

Reference clock input

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STR71XF 数据表(PDF) 24 Page - STMicroelectronics

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