M41T94 datasheet(11/31 Pages) STMICROELECTRONICS

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M41T94

OPERATION

The M41T94 clock operates as a slave device on

the SPI serial bus. Each memory device is access-

ed by a simple serial interface that is SPI bus com-

patible. The bus signals are SCL, SDI and SDO

(see Table 1, page 5 and Figure 7, page 6). The

device is selected when the Chip Enable input (E)

is held low. All instructions, addresses and data

are shifted serially in and out of the chip. The most

significant bit is presented first, with the data input

(SDI) sampled on the first rising edge of the clock

(SCL) after the Chip Enable (E) goes low. The 64

bytes contained in the device can then be access-

ed sequentially in the following order:

Tenths/Hundredths of a Second Register

Seconds Register

Minutes Register

Century/Hours Register

Day Register

Date Register

Month Register

Year Register

Control Register

10.

Watchdog Register

11 - 16.Alarm Registers

17 - 19.Reserved

20.

Square Wave Register

21 - 64.User RAM

The M41T94 clock continually monitors VCC for an

out-of tolerance condition. Should VCC fall below

VPFD, the device terminates an access in progress

and resets the device address counter. Inputs to

the device will not be recognized at this time to

prevent erroneous data from being written to the

device from a an out-of-tolerance system. When

VCC falls below VSO, the device automatically

switches over to the battery and powers down into

an ultra low current mode of operation to conserve

battery life. As system power returns and VCC ris-

es above VSO, the battery is disconnected, and the

power supply is switched to external VCC. Write

protection continues until VCC reaches VPFD (min)

plus tREC (min). For more information on Battery

Storage Life refer to Application Note AN1012.

SPI Bus Characteristics

The Serial Peripheral interface (SPI) bus is intend-

ed for synchronous communication between dif-

ferent ICs. It consists of four signal lines: Serial

Data Input (SDI), Serial Data Output (SDO), Serial

Clock (SCL) and a Chip Enable (E).

By definition a device that gives out a message is

called “transmitter,” the receiving device that gets

the message is called “receiver.” The device that

controls the message is called “master.” The de-

vices that are controlled by the master are called

“slaves.”

The E input is used to initiate and terminate a data

transfer. The SCL input is used to synchronize

data transfer between the master (micro) and the

slave (M41T94) devices.

The SCL input, which is generated by the micro-

controller, is active only during address and data

transfer to any device on the SPI bus (see Figure

7, page 6).

The M41T94 can be driven by a microcontroller

with its SPI peripheral running in either of the two

following modes:

(CPOL, CPHA) = ('0', '0') or

(CPOL, CPHA) = ('1', '1').

For these two modes, input data (SDI) is latched in

by the low-to-high transition of clock SCL, and out-

put data (SDO) is shifted out on the high-to-low

transition of SCL (see Table 2, page 7 and Figure

8, page 7).

There is one clock for each bit transferred. Ad-

dress and data bits are transferred in groups of

eight bits. Due to memory size the second most

significant address bit is a Don’t Care (address bit

6).

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