M41T94 datasheet(16/31 Pages) STMICROELECTRONICS

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M41T94

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Table 9. Power Down/Up AC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).

2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until

200µs after VCC passes VPFD (min).

3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

4. At 25°C, VCC = 0V (when using SOH28 + M4T28-BR12SH SNAPHAT top).

5. Programmable (see Table 14, page 23)

CLOCK OPERATIONS

The eight byte clock register (see Table 10, page

17) is used to both set the clock and to read the

date and time from the clock, in a binary coded

decimal format. Tenths/Hundredths of Seconds,

Seconds, Minutes, and Hours are contained within

the first four registers. Bits D6 and D7 of Clock

CENTURY ENABLE Bit (CEB) and the CENTURY

Bit (CB). Setting CEB to a '1' will cause CB to tog-

gle, either from '0' to '1' or from '1' to '0' at the turn

of the century (depending upon its initial state). If

CEB is set to a '0,' CB will not toggle. Bits D0

through D2 of Register 04h contain the Day (day

of week). Registers 05h, 06h, and 07h contain the

Date (day of month), Month and Years. The ninth

clock register is the Control Register (this is de-

scribed in the Clock Calibration section). Bit D7 of

this bit to a '1' will cause the oscillator to stop. If the

device is expected to spend a significant amount

of time on the shelf, the oscillator may be stopped

to reduce current drain. When reset to a '0' the os-

cillator restarts within one second.

The eight Clock Registers may be read one byte at

a time, or in a sequential block. The Control Reg-

ister (Address location 08h) may be accessed in-

dependently. Provision has been made to assure

that a clock update does not occur while any of the

eight clock addresses are being read. If a clock ad-

dress is being read, an update of the clock regis-

ters will be halted. This will prevent a transition of

data during the READ.

Note: When a power failure occurs, the Halt Up-

date Bit (HT) will automatically be set to a '1.' This

will prevent the clock from updating the clock reg-

isters, and will allow the user to read the exact time

of the power-down event. Resetting the HT Bit to

a '0' will allow the clock to update the clock regis-

ters with the current time.

TIMEKEEPER® Registers

The M41T94 offers 20 internal registers which

contain Clock, Alarm, Watchdog, Flag, Square

Wave and Control data (see Table 10, page 17).

These registers are memory locations which con-

tain external (user accessible) and internal copies

of the data (usually referred to as BiPORT™ TIME-

KEEPER cells). The external copies are indepen-

dent of internal functions except that they are

updated periodically by the simultaneous transfer

of the incremented internal copy. The internal di-

vider (or clock) chain will be reset upon the com-

pletion of a WRITE to any clock address.

The system-to-user transfer of clock data will be

halted whenever the clock addresses (00h to 07h)

are being written. The update will resume either

due to a deselect condition or when the pointer in-

crements to a non-clock or RAM address.

TIMEKEEPER and Alarm Registers store data in

BCD. Control, Watchdog and Square Wave Reg-

isters store data in Binary format.

Symbol

Parameter(1)

Min

Typ

Max

Unit

(2)

VPFD (max) to VPFD (min) VCC Fall Time

300

µs

tFB

(3)

VPFD (min) to VSS VCC Fall Time

µs

VPFD (min) to VPFD (max) VCC Rise Time

µs

tRB

VSS to VPFD (min) VCC Rise Time

1µs

tREC

(5)

Power up Deselect Time

200

tDR

Expected Data Retention Time

10(4)

YEARS

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