M41T94 datasheet(22/31 Pages) STMICROELECTRONICS

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M41T94

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Calibrating the Clock

The M41T94 is driven by a quartz-controlled oscil-

lator with a nominal frequency of 32,768 Hz. Un-

calibrated clock accuracy will not exceed ±35 PPM

(parts per million) oscillator frequency error at

25°C, which equates to about ±1.53 minutes per

month. When the Calibration circuit is properly em-

ployed, accuracy improves to better than +1/–2

PPM at 25°C.

The oscillation rate of crystals changes with tem-

perature (see Figure 18, page 24). Therefore, the

M41T94 design employs periodic counter correc-

tion. The calibration circuit adds or subtracts

counts from the oscillator divider circuit at the di-

vide by 256 stage, as shown in Figure 19, page 24.

The number of times pulses are blanked (subtract-

ed, negative calibration) or split (added, positive

calibration) depends upon the value loaded into

the five Calibration Bits found in the Control Reg-

ister. Adding counts speeds the clock up, subtract-

ing counts slows the clock down.

The Calibration Bits occupy the five lower order

bits (D4-D0) in the Control Register (8h). These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 minutes in the cycle may, once

per minute, have one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minutes in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 PPM of adjustment per calibra-

tion step in the calibration register. Assuming that

the oscillator is running at exactly 32,768 Hz, each

of the 31 increments in the Calibration byte would

represent +10.7 or –5.35 seconds per month

which corresponds to a total range of +5.5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M41T94 may require.

The first involves setting the clock, letting it run for

a month and comparing it to a known accurate ref-

erence and recording deviation over a fixed period

of time. Calibration values, including the number of

seconds lost or gained in a given period, can be

found in Application Note AN934: TIMEKEEPER

CALIBRATION. This allows the designer to give

the end user the ability to calibrate the clock as the

environment requires, even if the final product is

packaged in a non-user serviceable enclosure.

The designer could provide a simple utility that ac-

cesses the Calibration Byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT/OUT pin. The pin will toggle at 512 Hz,

when the Stop Bit (ST, D7 of 1h) is '0,' the Fre-

quency Test Bit (FT, D6 of 8h) is '1,' the Alarm Flag

Enable Bit (AFE, D7 of Ah) is '0,' and the Watch-

dog Steering Bit (WDS, D7 of 9h) is '1' or the

Watchdog Register (9h = 0) is reset.

Any deviation from 512 Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature.

For

example,

reading

512.010124 Hz would indicate a +20 PPM oscilla-

tor frequency error, requiring a –10 (XX001010) to

be loaded into the Calibration Byte for correction.

Note: Setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency.

The IRQ/FT/OUT pin is an open drain output

which requires a pull-up resistor for proper opera-

tion. A 500 to 10k

Ω resistor is recommended in or-

der to control the rise time. The FT Bit is cleared

on power-down.

Century Bit

Bits D7 and D6 of Clock Register 03h contain the

CENTURY ENABLE Bit (CEB) and the CENTURY

Bit (CB). Setting CEB to a '1' will cause CB to tog-

gle, either from a '0' to '1' or from '1' to '0' at the turn

of the century (depending upon its initial state). If

CEB is set to a '0,' CB will not toggle.

Output Driver Pin

When the FT Bit, AFE Bit and Watchdog Register

are not set, the IRQ/FT/OUT pin becomes an out-

put driver that reflects the contents of D7 of the

Control Register. In other words, when D7 (OUT

Bit) and D6 (FT Bit) of address location 08h are a

'0,' then the IRQ/FT/OUT pin will be driven low.

Note: The IRQ/FT/OUT pin is an open drain which

requires an external pull-up resistor.

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