M48T35 datasheet(8/18 Pages) STMICROELECTRONICS

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M48T35, M48T35Y

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Table 10. Write Mode AC Characteristics

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

Note: 1. CL = 5pF.

2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Symbol

Parameter

M48T35 / M48T35Y

Unit

-70

Min

Max

tAVAV

Write Cycle Time

tAVWL

Address Valid to Write Enable Low

tAVEL

Address Valid to Chip Enable Low

tWLWH

Write Enable Pulse Width

tELEH

Chip Enable Low to Chip Enable High

tWHAX

Write Enable High to Address Transition

tEHAX

Chip Enable High to Address Transition

tDVWH

Input Valid to Write Enable High

tDVEH

Input Valid to Chip Enable High

tWHDX

Write Enable High to Input Transition

tEHDX

Chip Enable High to Input Transition

tWLQZ

(1, 2)

Write Enable Low to Output Hi-Z

tAVWH

Address Valid to Write Enable High

tAVEH

Address Valid to Chip Enable High

tWHQX

(1, 2)

Write Enable High to Output Transition

DATA RETENTION MODE

With valid VCC applied, the M48T35/35Y operates

as a conventional BYTEWIDE static RAM. Should

the supply voltage decay, the RAM will automati-

cally power-fail deselect, write protecting itself

when VCC falls within the VPFD (max), VPFD (min)

window. All outputs become high impedance, and

all inputs are treated as "don't care."

Note: A power failure during a write cycle may cor-

rupt data at the currently addressed location, but

does not jeopardize the rest of the RAM's content.

At voltages below VPFD (min), the user can be as-

sured the memory will be in a write protected state,

provided the VCC fall time is not less than tF. The

M48T35/35Y may respond to transient noise

spikes on VCC that reach into the deselect window

during the time the device is sampling VCC. There-

fore, decoupling of the power supply lines is rec-

ommended.

When VCC drops below VSO, the control circuit

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button cell will maintain data in the M48T35/35Y

for an accumulated period of at least 7 years when

VCC is less than VSO. As system power returns

and VCC rises above VSO, the battery is discon-

nected, and the power supply is switched to exter-

nal VCC. Write protection continues until VCC

reaches VPFD (min) plus tREC (min). E should be

kept high as VCC rises past VPFD (min) to prevent

inadvertent write cycles prior to processor stabili-

zation. Normal RAM operation can resume tREC

after VCC exceeds VPFD (max).

For more information on Battery Storage Life refer

to the Application Note AN1012.

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