M48T35, M48T35Y

4/18

The clock locations contain the year, month, date,

day, hour, minute, and second in 24 hour BCD for-

mat. Corrections for 28, 29 (leap year), 30, and 31

day months are made automatically. Byte 7FF8h

is the clock control register. This byte controls user

access to the clock information and also stores the

clock calibration setting.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT read/write memory cells.

The M48T35/35Y includes a clock control circuit

which updates the clock bytes with current infor-

mation once per second. The information can be

accessed by the user in the same manner as any

other location in the static memory array.

The M48T35/35Y also has its own Power-fail De-

tect circuit. The control circuitry constantly moni-

tors the single 5V supply for an out of tolerance

write protects the SRAM, providing a high degree

of data security in the midst of unpredictable sys-

below approximately 3V, the control circuitry con-

nects the battery which maintains data and clock

operation until valid power returns.

READ MODE

The M48T35/35Y is in the Read Mode whenever

W (Write Enable) is high and E (Chip Enable) is

low. The unique address specified by the 15 Ad-

dress Inputs defines which one of the 32,768 bytes

of data is to be accessed. Valid data will be avail-

able at the Data I/O pins within Address Access

stable, providing that the E and G access times

are also satisfied.

If the E and G access times are not met, valid data

will be available after the latter of the Chip Enable

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

If the Address Inputs are changed while E and G

remain active, output data will remain valid for Out-

nate until the next Address Access.

WRITE MODE

The M48T35/35Y is in the Write Mode whenever

W and E are low. The start of a write is referenced

from the latter occurring falling edge of W or E. A

write is terminated by the earlier rising edge of W

or E. The addresses must be held valid throughout

the cycle. E or W must return high for a minimum

able prior to the initiation of another read or write

should be kept high during write cycles to avoid

bus contention; although, if the output bus has

been activated by a low on E and G, a low on W

Table 4. AC Measurement Conditions

Note that Output Hi-Z is defined as the point where data is no longer

driven.

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0 to 3V

Input and Output Timing Ref. Voltages

1.5V

Figure 4. AC Testing Load Circuit

AI01030

5V

OUT

CL = 100pF or 5pF

CL includes JIG capacitance

1.9k

Ω

DEVICE

UNDER

TEST

1k

Ω