11/18

M48T35, M48T35Y

Two methods are available for ascertaining how

much calibration a given M48T35/35Y may re-

quire. The first involves simply setting the clock,

letting it run for a month and comparing it to a

known accurate reference (like WWV broadcasts).

While that may seem crude, it allows the designer

to give the end user the ability to calibrate his clock

as his environment may require, even after the fi-

nal product is packaged in a non-user serviceable

enclosure.

All the designer has to do is provide a simple utility

that accesses the Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of

some test equipment. When the Frequency Test

(FT) bit, the seventh-most significant bit in the Day

Register is set to a ’1’, and D7 of the Seconds Reg-

ister is a ’0’ (Oscillator Running), DQ0 will toggle at

512Hz during a read of the Seconds Register. Any

deviation from 512 Hz indicates the degree and di-

rection of oscillator frequency shift at the test tem-

perature. For example, a reading of 512.01024 Hz

would indicate a +20 ppm oscillator frequency er-

ror, requiring a –10 (WR001010) to be loaded into

the Calibration Byte for correction. Note that set-

ting or changing the Calibration Byte does not af-

fect

the

Frequency

test

output

frequency.

The FT bit MUST be reset to '0' for normal clock

operations to resume. The FT bit is automatically

Reset on power-up.

For more information on calibration, see the Appli-

cation Note AN934 "TIMEKEEPER Calibration".

Most clock chips compensate for crystal frequency

and temperature shift error with cumbersome trim

capacitors. The M48T35/35Y design, however,

employs periodic counter correction. The calibra-

tion circuit adds or subtracts counts from the oscil-

lator divider circuit at the divide by 256 stage, as

shown in Figure 9. The number of times pulses are

blanked (subtracted, negative calibration) or split

(added, positive calibration) depends upon the

value loaded into the five Calibration bits found in

the Control Register. Adding counts speeds the

clock up, subtracting counts slows the clock down.

The Calibration byte occupies the five lower order

bits (D4-D0) in the Control Register 7FF8h. These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 minutes in the cycle may, once

per minute, have one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minutes in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step in the calibration register. Assuming that

the oscillator is in fact running at exactly 32,768

Hz, each of the 31 increments in the Calibration

byte would represent +10.7 or –5.35 seconds per

month which corresponds to a total range of +5.5

or –2.75 minutes per month.

Figure 9. Clock Calibration

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION