STA328 datasheet(10/57 Pages) STMICROELECTRONICS

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Pin out

STA328

10/57

I2C

signals (pins 23 and 24)

The SDA (I2C Data) and SCL (I2C Clock) pins operate according to the I2C specification

(Chapter 5 on page 16 gives more information). Fast-mode (400 kB/s) I2C communication is

supported.

GNDA and VDDA (pins 28 and 29)

This is the 3.3 V analog supply for the phase locked loop. It must be well decoupled and

filtered for good noise immunity since the audio performance of the device depends upon

the PLL circuit.

CLK (pin 27)

This is the master clock in used by the digital core. The master clock must be an integer

multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz

(256 * fs) for a 48 kHz sample rate; it is the default setting at power-up. Care must be taken

to provide the device with the nominal system clock frequency; over-clocking the device may

result in anomalous operation, such as inability to communicate.

FILTER_PLL (pin 26)

This is the connection for external filter components for the PLL loop compensation. The

schematic diagram in Figure 5 on page 7 shows the recommended circuit.

BICKI (pin 32)

The serial or bit clock input is for framing each data bit. The bit clock frequency is typically

64 * fs using I2S serial format.

SDI_12 (pin 30)

This is the serial data input where PCM audio information enters the device. Six format

choices are available including I2S, left or right justified, LSB or MSB first, with word widths

of 16, 18, 20 and 24 bits.

LRCKI (pin 31)

The left/right clock input is for data word framing. The clock frequency is at the input sample

rate, fs.

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