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STA328 数据表(PDF) 17 Page - STMicroelectronics

部件名 STA328
功能描述  2.1-channel high-efficiency digital audio system
PDF  57 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA328 数据表(HTML) 17 Page - STMicroelectronics

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STA328
I2C bus specification
17/57
5.3
Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA328 acknowledges this and then the master writes the internal address byte.
After receiving the internal byte address the STA328 again responds with an
acknowledgement.
Figure 13.
I2C write procedure
Byte write
In the byte write mode the master sends one data byte. This is acknowledged by the
STA328. The master then terminates the transfer by generating a STOP condition.
Multi-byte write
The multi-byte write modes can start from any internal address. Sequential data byte writes
will be written to sequential addresses within the STA328.
The master generating a STOP condition terminates the transfer.
5.4
Read operation
Figure 14.
I2C read procedure
Current address byte read
Following the START condition the master sends a device select code with the RW bit set to
1. The STA328 acknowledges this and then responds by sending one byte of data. The
master then terminates the transfer by generating a STOP condition.
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
BYTE
WRITE
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
MULTIBYTE
WRITE
DATA IN
ACK
DEV-ADDR
ACK
START
RW
DATA
NO ACK
STOP
CURRENT
ADDRESS
READ
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
STOP
RANDOM
ADDRESS
READ
DATA
NO ACK
START
RW
DEV-ADDR
ACK
START
DATA
ACK
DATA
ACK
STOP
SEQUENTIAL
CURRENT
READ
DATA
NO ACK
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
SEQUENTIAL
RANDOM
READ
DATA
ACK
START
RW
DATA
ACK
NO ACK
STOP
DATA
RW=
HIGH



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