APM32F103TBU6-R datasheet(23/78 Pages) GEEHY

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4.6.3

Power monitor

Power-on reset (POR) and power-down reset (PDR) circuits are integrated inside the product.

When VDD reaches the set threshold VPOR/PDR, the system works normally; when the VDD is

lower than the set threshold VPOR/PDR, the system will remain in the reset state without

connecting the external reset circuit.

4.7

Low-power mode

The product supports three low-power modes. Users can switch between these modes by

setting.

Table8 Low-power Mode

Mode

Description

Sleep mode

In sleep mode, all peripherals are in working status, but the CPU stops working. If an

interrupt/event occurs, the CPU will be waked up.

Stop mode

The stop mode is the mode that can achieve the lowest power consumption without losing

the content of SRAM and register. At this time, internal 1.6V power supply stops, causing

the HSECLK, HSICLK and PLL clocks to turn off, and the voltage regulator is set to the

normal mode or low-power mode. Interrupt and event wake-up configured as EINT can

wake the CPU from the stop mode. EINT signal includes 16 external I/O ports, PVD

output, RTC alarm or USBD wake-up signal.

Standby

mode

The standby mode is the lowest-power mode used by the chip. At this time, the internal

voltage regulator is disabled, causing power supply of the internal 1.6V part to be cut off;

HSECLK, HSICLK and PLL clocks are disabled; the content of SRAM and register will

disappear. However, the content of the backup register will remain and the standby circuit

will still work.

The external reset signal on NRST, IWDT reset, a rising edge on WKUP pin or RTC alarm

will terminate the standby mode of the chip.

Note: When entering the stop or standby mode, RTC, IWDT and corresponding clock will not

stop, and the interrupt of QSPI cannot wake up the low power.

4.8

DMA

The product has 7-channel general-purpose DMA, which can manage the data transmission

from memory to memory, device to memory, and memory to device.

Each channel has hardware DMA request logic, and the source address, destination address

and transmission length of each channel can be set separately by software.

DMA can be used for main peripherals: SPI, I2C, USART, timer TMRx and ADC, QSPI.

4.9

GPIO

The product can have up to 80 GPIO pins. Every pin can be switched between input (pull-up,

pull-down), output (push-pull, open-drain) or multiplexing functions through software

configuration. Most GPIO pins are shared with multiplexed peripherals. To avoid accidental

writing of I/O registers, the peripheral functions of I/O pins can be locked by specific

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